#include "string.h"
#include <sstream>
#include "Parameters.h"
+#include "DelayInputModifier.h"
int GroupBlock::counter = 1;
-GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() {
+GroupBlock::GroupBlock(GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock() {
GroupInterface* clk = NULL;
GroupInterface* rst = NULL;
}
}
+QList<QString> GroupBlock::getExternalResources() {
+
+ QList<QString> list;
+ foreach(AbstractBlock* block, blocks) {
+ list.append(block->getExternalResources());
+ }
+ return list;
+}
+
void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
QString coreFile = "";
- coreFile = path;
+ coreFile = path;
coreFile.append(Parameters::normalizeName(name));
coreFile.append(".vhd");
generateLibraries(outCore,dummyElt);
generateEntity(outCore);
generateArchitecture(outCore,dummyElt);
+
+ foreach(AbstractBlock* block, blocks) {
+ block->generateVHDL(path);
+ }
}
catch(Exception err) {
throw(err);
out << "architecture rtl of " << name << " is " << endl << endl;
+ // generate type for delays, if needed.
+ QList<int> modWidth;
+ foreach(AbstractBlock* block, blocks) {
+ QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+ foreach(AbstractInterface* iface, listCtlInputs) {
+ ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+ AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+ if (modifier != NULL) {
+ ConnectedInterface* connIface = AI_TO_CON(connCtlIface->getAssociatedIface());
+ int w = connIface->getWidth();
+ if (w == -1) throw(Exception(INVALID_VALUE));
+ if (!modWidth.contains(w)) {
+ modWidth.append(w);
+ }
+ }
+ }
+ }
+ if (modWidth.size() > 0) {
+
+ out << " -- types for modified inputs" << endl;
+ out << " type vector_of_std_logic is array (natural range <>) of std_logic;" << endl;
+ foreach(int w, modWidth) {
+ QString mw = "";
+ mw.setNum(w);
+ QString mwm1 = "";
+ mwm1.setNum(w-1);
+ out << " type vector_of_std_logic_vector"<< mw << " is array (natural range <>) of std_logic_vector(" << mwm1 << " downto 0);" << endl;
+ }
+ out << endl;
+ }
+
+
// generate the components
foreach(AbstractBlock* block, blocks) {
try {
out << endl;
// generate signals
out << " ----------------------------" << endl;
- out << " SIGNALS" << endl;
+ out << " -- SIGNALS" << endl;
out << " ----------------------------" << endl << endl;
+ // signals to synchronize inputs
+ out << " -- signals to synchronize inputs" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ QString name = iface->toVHDL(AbstractInterface::Signal,0);
+ name.replace(" : ","_sync : ");
+ out << " signal " << name<< endl;
+ }
+ }
+ out << endl;
+ // "normal" signals
foreach(AbstractBlock* block, blocks) {
try {
out << " -- signals from output ports of " << block->getName() << endl;
}
out << endl;
}
+
+ // signal for modifiers
foreach(AbstractBlock* block, blocks) {
- try {
- out << " -- signals for modified input ports of " << block->getName() << endl;
- QList<AbstractInterface*> listInputs = block->getInputs();
- foreach(AbstractInterface* iface, listInputs) {
- if (iface->getPurpose() == AbstractInterface::Control) {
+ bool hasModif = false;
+ QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+
+ foreach(AbstractInterface* iface, listCtlInputs) {
+ ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+ AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+ if (modifier != NULL) {
+ hasModif = true;
+ break;
+ }
+ }
+ if (hasModif) {
+ try {
+ out << " -- signals for modified input ports of " << block->getName() << endl;
+ foreach(AbstractInterface* iface, listCtlInputs) {
ConnectedInterface* connCtlIface = AI_TO_CON(iface);
AbstractInputModifier* modifier = connCtlIface->getInputModifier();
if (modifier != NULL) {
}
}
}
+ catch(Exception e) {
+ throw(e);
+ }
+ out << endl;
}
- catch(Exception e) {
- throw(e);
- }
- out << endl;
}
out << "begin" << endl;
}
}
else if (fromIface->isGroupInterface()) {
- portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+ portMap += " " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+ }
+ else {
+ portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ }
}
}
if (listOutputs.size()>0) {
}
}
+ if (topGroup) {
+ // generate input sync process
+ out << " -- process to synchronize inputs of top group" << endl;
+ out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+ out << " begin" << endl;
+ out << " if from_clkrstgen_reset = '1' then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+ }
+ }
+ }
+ out << " elsif rising_edge(from_clkrstgen_clk) then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ }
+ }
+ out << " end if;" << endl;
+ out << " end process sync_inputs;" << endl;
+
+ out << endl;
+ }
+
out << "end architecture rtl;" << endl;
}