finalized analysis with clkconvert + started testbench gen.

[blast.git] / Graph.cpp

diff --git a/Graph.cpp b/Graph.cpp
index 4b22691ff97492ba3bf853d1f49563ccf2b08479..d0c11cc30907263705db2dc8521183dab7d9ea35 100644 (file)
--- a/Graph.cpp
+++ b/Graph.cpp
@@ -4,10 +4,8 @@
 #include "FunctionalBlock.h"
 #include "SpecialBlock.h"
 
-Graph::Graph(bool createTopGroupIface) {
-  topGroup = new GroupBlock(NULL, createTopGroupIface);
-  topGroup->setName("top group");
-  groups.append(topGroup);
+Graph::Graph() {
+  topGroup = NULL;
 }
 
 Graph::~Graph() {
@@ -15,12 +13,18 @@ Graph::~Graph() {
   delete topGroup;
 }
 
+void Graph::createTopGroup(bool createTopGroupIfaces) {
+  topGroup = new GroupBlock(this, NULL, createTopGroupIfaces);
+  topGroup->setName("top group");
+  groups.append(topGroup);
+}
+
 QList<AbstractInterface *> Graph::getOutsideInterfaces() {
   return topGroup->getInterfaces();
 }
 
 GroupBlock* Graph::createChildGroupBlock(GroupBlock* parent, bool createGroupIface) {
-  GroupBlock* b = new GroupBlock(parent, createGroupIface);
+  GroupBlock* b = new GroupBlock(this, parent, createGroupIface);
   groups.append(b);
   return b;
 }
@@ -42,11 +46,13 @@ GroupBlock* Graph::getGroupBlockByName(QString name) {
 FunctionalBlock* Graph::createFunctionalBlock(GroupBlock* group, ReferenceBlock* ref, bool createIfaces) {
 
   FunctionalBlock* newBlock = NULL;
-  if (ref->getSpecialType() != -1) {
-    newBlock = new SpecialBlock(ref->getSpecialType(), group,ref, createIfaces);
+  if (ref->getSpecialType() != SpecialBlock::NotSpecial) {
+    cout << "Graph: create special block from " << qPrintable(ref->getName()) << endl;
+    newBlock = new SpecialBlock(this, ref->getSpecialType(), group,ref, createIfaces);
   }
   else {
-    newBlock = new FunctionalBlock(group,ref, createIfaces);
+    cout << "Graph: create normal block from " << qPrintable(ref->getName()) << endl;
+    newBlock = new FunctionalBlock(this, group,ref, createIfaces);
   }
   group->addBlock(newBlock);
 
@@ -87,7 +93,7 @@ FunctionalBlock* Graph::getFunctionalBlockByName(QString name, GroupBlock* paren
 FunctionalBlock* Graph::createStimuliBlock(ReferenceBlock* ref, bool createIfaces) {
   /* A stimuli block is always a special block with idSpecial = 1 */
 
-  FunctionalBlock* newBlock = new SpecialBlock(AbstractBlock::Source, NULL,ref, createIfaces);
+  FunctionalBlock* newBlock = new SpecialBlock(this, AbstractBlock::Source, NULL,ref, createIfaces);
   stimulis.append(newBlock);
   return newBlock;
 }
@@ -200,6 +206,18 @@ void Graph::computeOutputPatterns(int nbExec) throw(Exception) {
 }
 
 void Graph::generateVHDL(const QString &path) throw(Exception) {
+  // generating VHDL for stimulis
+  cout << "generating stimulis" << endl;
+  try {
+    foreach(FunctionalBlock* stimuli, stimulis) {
+      stimuli->generateVHDL(path);
+    }
+  }
+  catch(Exception e) {
+    throw(e);
+  }
+  // generating VHDL for top group
+  cout << "generating top group" << endl;
   try {
     topGroup->generateVHDL(path);
   }
@@ -208,6 +226,72 @@ void Graph::generateVHDL(const QString &path) throw(Exception) {
   }
 }
 
+void Graph::generateTestbench(const QString &projectName, const QString &benchFile) throw(Exception) {
+
+
+  QFile vhdlBench(benchFile);
+
+  if (!vhdlBench.open(QIODevice::WriteOnly)) {
+    throw(Exception(VHDLFILE_NOACCESS));
+  }
+
+  cout << "generate testbench" << endl;
+  QTextStream out(&vhdlBench);
+
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- testbench for " << projectName << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- clock generator" << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+
+  out << "library IEEE;" << endl;
+  out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+  out << "use IEEE.numeric_std.all;" << endl;
+  out << "entity clock_gen is" << endl;
+  out << "  generic (" << endl;
+  out << "    Tps : time                          -- high level width : must be < period" << endl;
+  out << "    );" << endl;
+  out << "  port (" << endl;
+  out << "    phase : out std_logic" << endl;
+  out << "    );" << endl;
+  out << "end entity clock_gen;"  << endl<< endl;
+
+  out << "architecture clock_gen_1 of clock_gen is" << endl;
+  out << "  constant period : time := 2*Tps;" << endl;
+  out << "begin" << endl;
+  out << "  clock_process : process" << endl;
+  out << "  begin" << endl;
+  out << "    phase <= '1', '0' after Tps;" << endl;
+  out << "    wait for period;" << endl;
+  out << "  end process clock_process;" << endl;
+  out << "end architecture clock_gen_1;" << endl << endl;
+
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- testbench" << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+  out << "library IEEE;" << endl;
+  out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+  out << "use IEEE.numeric_std.all;" << endl;
+  out << "entity " << projectName << "_tb is" << endl;
+  out << "end entity " << projectName << "_tb;" << endl << endl;
+  out << "architecture " << projectName << "_tb_1 of " << projectName << "_tb is" << endl << endl;
+
+  out << "  component clock_gen" << endl;
+  out << "    generic (" << endl;
+  out << "      Tps : time" << endl;
+  out << "      );" << endl;
+  out << "    port (" << endl;
+  out << "      phase : out std_logic" << endl;
+  out << "      );" << endl;
+  out << "  end component;" << endl << endl;
+
+  topGroup->generateComponent(out,false);
+
+  vhdlBench.close();
+
+}
+
 QList<QString> Graph::getExternalResources() {
   QList<QString> list = topGroup->getExternalResources();
   return list;