finished testbench generation

[blast.git] / lib / references / clkdomain_convert_1024x8.xml

diff --git a/lib/references/clkdomain_convert_1024x8.xml b/lib/references/clkdomain_convert_1024x8.xml
index b980f69c24b845f2ddd9590daa5e64dfe1edb007..59f84edccaf6c1aa23b0c88289b077412686ffe9 100644 (file)
--- a/lib/references/clkdomain_convert_1024x8.xml
+++ b/lib/references/clkdomain_convert_1024x8.xml
@@ -7,20 +7,17 @@
       This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.
     </description>
   </informations>
       This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.
     </description>
   </informations>

-  <parameters>
-    <parameter type="real" context="generic" name="clk_in_freq" value="100"/>
-    <parameter type="real" context="generic" name="clk_out_freq" value="100"/>
-  </parameters>
+  <parameters />

   <interfaces>
     <inputs>
   <interfaces>
     <inputs>

-      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_rd" purpose="clock"/>
-      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_wr" purpose="clock"/>
-      <input width="1" multiplicity="1" endian="little" type="boolean" name="reset" purpose="reset"/>
-      <input width="8" multiplicity="1" endian="little" type="natural" name="data_in" purpose="data" clock="clk_rd"/>
+      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_in" purpose="clock"/>
+      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_out" purpose="clock"/>
+      <input width="1" multiplicity="1" endian="little" type="boolean" name="reset" purpose="reset" clock="clk_in"/>
+      <input width="8" multiplicity="1" endian="little" type="natural" name="data_in" purpose="data" clock="clk_in"/>

       <control iface="data_in"/>
     </inputs>
     <outputs>
       <control iface="data_in"/>
     </inputs>
     <outputs>

-      <output width="8" multiplicity="1" endian="little" type="natural" name="data_out" purpose="data" clock="clk_wr"/>
+      <output width="8" multiplicity="1" endian="little" type="natural" name="data_out" purpose="data" clock="clk_out"/>

       <control iface="data_out"/>
     </outputs>
   </interfaces>
       <control iface="data_out"/>
     </outputs>
   </interfaces>