finalized analysis with clkconvert + started testbench gen.

[blast.git] / lib / implementations / clkdomain_convert_1024x8_impl.xml

diff --git a/lib/implementations/clkdomain_convert_1024x8_impl.xml b/lib/implementations/clkdomain_convert_1024x8_impl.xml
index cdab60b298d5619ee5ce3b7cb6497daadaf3dad1..6046ebea0be755346aab416143e088acbc908df5 100644 (file)
--- a/lib/implementations/clkdomain_convert_1024x8_impl.xml
+++ b/lib/implementations/clkdomain_convert_1024x8_impl.xml
@@ -2,11 +2,10 @@
 <block_impl ref_name="clkdomain_convert_1024x8.xml" ref_md5="">
   <comments>
     <author mail="sdomas@univ-fcomte.fr" lastname="domas" firstname="stephane"/>
 <block_impl ref_name="clkdomain_convert_1024x8.xml" ref_md5="">
   <comments>
     <author mail="sdomas@univ-fcomte.fr" lastname="domas" firstname="stephane"/>

-    <date creation="2018-04-13"/>
-    <related_files list=""/>
-    <description>This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.
-</description>
-    <notes>This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.</notes>
+    <log creation="2018-05-02">
+    </log>
+    <notes>
+    </notes>

   </comments>
   <libraries>
     <library name="ieee">
   </comments>
   <libraries>
     <library name="ieee">


@@ -38,8 +37,8 @@ begin
 clkdconvert_1024x8_1 : clkdconvert_1024x8
 port map (
 rst => @{reset},
 clkdconvert_1024x8_1 : clkdconvert_1024x8
 port map (
 rst => @{reset},

-wr_clk => @{clk_wr},
-rd_clk => @{clk_rd},
+wr_clk => @{clk_in},
+rd_clk => @{clk_out},

 din => @{data_in},
 wr_en => @{data_in_enb},
 rd_en => rd_en,
 din => @{data_in},
 wr_en => @{data_in_enb},
 rd_en => rd_en,


@@ -50,11 +49,11 @@ empty => empty
 
 rd_en &lt;= not empty;
 
 
 rd_en &lt;= not empty;
 

-read_fifo : process(@{clk_rd}, @{reset})
+read_fifo : process(@{clk_out}, @{reset})

 begin
 if @{reset} = '1' then
 @{data_out_enb} &lt;= '0';
 begin
 if @{reset} = '1' then
 @{data_out_enb} &lt;= '0';

-elsif rising_edge(@{clk_rd}) then
+elsif rising_edge(@{clk_out}) then

 @{data_out_enb} &lt;= '0';
 if empty = '0' then
 @{data_out_enb} &lt;= '1';
 @{data_out_enb} &lt;= '0';
 if empty = '0' then
 @{data_out_enb} &lt;= '1';