finished VHDL gen

[blast.git] / lib / references / apf27-wb-master.xml

diff --git a/lib/references/apf27-wb-master.xml b/lib/references/apf27-wb-master.xml
index 82ee08afc4441ed29cf4162f5522b01eaa3b5bd8..777424e857baaabd2629ee20e47e190f7054e2c2 100644 (file)
--- a/lib/references/apf27-wb-master.xml
+++ b/lib/references/apf27-wb-master.xml
@@ -2,9 +2,9 @@
 <block>
   <informations>
     <name>
-      wishbone master for apf27
+      apf27_wb_master
     </name>
-    <category ids="1,4" />  
+    <category ids="100" />  
     <description>
       <brief>
        This block is the wishbone master of the design, connected to the i.MX of APF27
@@ -23,10 +23,10 @@
       <input name="clk" type="boolean" width="1" purpose="clock" />
       <input name="rst" type="boolean" width="1" purpose="reset" />
       
-      <input name="imx_addr" type="expression" width="$wb_addr_width" level="top"/>
-      <input name="imx_cs_n" type="boolean" width="1" level="top"/>
-      <input name="imx_oe_n" type="boolean" width="1" level="top"/>
-      <input name="imx_eb3_n" type="boolean" width="1" level="top"/>
+      <input name="imx_addr" type="expression" width="$wb_addr_width" />
+      <input name="imx_cs_n" type="boolean" width="1" />
+      <input name="imx_oe_n" type="boolean" width="1" />
+      <input name="imx_eb3_n" type="boolean" width="1" />
       
       <input name="ack_i" type="boolean" width="1" purpose="wb" />
       <input name="dat_i" width="$wb_data_width" purpose="wb" />
@@ -39,7 +39,7 @@
       <output name="we_o" type="boolean" width="1" purpose="wb" />
     </outputs>
     <bidirs>
-      <bidir name="imx_data" width="$wb_data_width" level="top"/>
+      <bidir name="imx_data" width="$wb_data_width"/>
     </bidirs>
   </interfaces>