enum IfaceDirection { AnyDirection = 0, Input = 1, Output = 2, InOut = 3 };
enum IfaceVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Instance = 3, Signal = 4 };
enum IfaceVHDLFlags { NoComma = 1 };
- enum IfaceClockName { NoName = 0, ClockName, ParameterName };
+ enum IfaceClockName { NoName = 0, ClockName, ParameterName, InheritedName };
static int getIntDirection(QString str);
static int getIntPurpose(QString str);
QString getDirectionString();
inline AbstractBlock *getOwner() { return owner;}
inline AbstractInterface* getAssociatedIface() { return associatedIface; }
- inline QString getClockIfaceString() { return clkIface; }
+ inline QString getClockIfaceString() { return clkIfaceName; }
inline int getClockIfaceType() { return clkIfaceType; }
AbstractInterface* getClockIface();
virtual int getClockDomain() throw(Exception) = 0; // determine on which clock domain is sync this interface
void setPurpose(int _purpose);
void setDirection(int _direction);
bool setAssociatedIface(AbstractInterface* iface);
- bool setClockIface(QString name);
+ inline void setClockIfaceType(int type) { clkIfaceType = type; }
+ inline void setClockIfaceName(QString name) { clkIfaceName = name; }
// testers
virtual bool isReferenceInterface();
* Nevertheless, the designer has the possibility to connect the block taht owns this interface to another clkrstgen block. Moreover,
* some blocks may have several clocks, e.g. dual port RAMs, FIFOs.
*/
- QString clkIface;
+ QString clkIfaceName;
int clkIfaceType; // 0 for not affected, 1 for clock input name, 2 for user param name
