finished VHDL gen

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 4746a7480b9db4d660c4e560eaa090e0533a5d8e..ab76563048265cd375aabeaeecff9a6d0f606f7b 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -5,6 +5,8 @@
 #include "GroupInterface.h"
 #include "string.h"
 #include <sstream>
 #include "GroupInterface.h"
 #include "string.h"
 #include <sstream>

+#include "Parameters.h"
+#include "DelayInputModifier.h"

 
 int GroupBlock::counter = 1;
 
 
 int GroupBlock::counter = 1;
 


@@ -20,8 +22,17 @@ GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) :  AbstractBlock()
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);

-    addInterface(clk);
-    addInterface(rst);    
+    addInterface(clk);    
+    addInterface(rst);
+
+    try {
+      connectClkReset();
+    }
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);
+    }

   }
   else {
     topGroup = true;
   }
   else {
     topGroup = true;


@@ -169,20 +180,22 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
       if (block->getControlOutputs().size() > 0) addIt = true;
     }
     else {
       if (block->getControlOutputs().size() > 0) addIt = true;
     }
     else {

-      // if the block has all its connected inputs that are connected to an intput of the group, add it too
-      addIt = true;
-      foreach(AbstractInterface* iface, block->getControlInputs()) {
-        //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
-        ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
-        //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
-        
-        if (connFrom == NULL) {
-          addIt = false;
-          break;
-        }
-        else if (connFrom->getOwner() != this) {
-          addIt = false;
-          break;
+      // if the block has all its connected control inputs that are connected to an intput of the group, add it too
+      if (block->getControlInputs().size() > 0) {
+        addIt = true;
+        foreach(AbstractInterface* iface, block->getControlInputs()) {
+          //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+          ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+          //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+          if (connFrom == NULL) {
+            addIt = false;
+            break;
+          }
+          else if (connFrom->getOwner() != this) {
+            addIt = false;
+            break;
+          }

         }
       }
     }
         }
       }
     }


@@ -264,12 +277,21 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
   }
 }
 
   }
 }
 

+QList<QString> GroupBlock::getExternalResources() {
+
+  QList<QString> list;
+  foreach(AbstractBlock* block, blocks) {
+    list.append(block->getExternalResources());
+  }
+  return list;
+}
+

 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 
 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 

-  coreFile = path;
-  coreFile.append(normalizeName(name));
+  coreFile = path;  
+  coreFile.append(Parameters::normalizeName(name));

   coreFile.append(".vhd");
 
   QFile vhdlCore(coreFile);
   coreFile.append(".vhd");
 
   QFile vhdlCore(coreFile);


@@ -278,13 +300,19 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
     throw(Exception(VHDLFILE_NOACCESS));
   }
 
     throw(Exception(VHDLFILE_NOACCESS));
   }
 

+  cout << "generate VHDL of block " << qPrintable(name) << " in " << qPrintable(coreFile) << endl;

   QTextStream outCore(&vhdlCore);
 
   QTextStream outCore(&vhdlCore);
 

+  QDomElement dummyElt;

   try {
   try {

-    generateComments(outCore);
-    generateLibraries(outCore);
+    generateComments(outCore,dummyElt,"");
+    generateLibraries(outCore,dummyElt);

     generateEntity(outCore);
     generateEntity(outCore);

-    generateArchitecture(outCore);
+    generateArchitecture(outCore,dummyElt);
+
+    foreach(AbstractBlock* block, blocks) {
+      block->generateVHDL(path);
+    }

   }
   catch(Exception err) {
     throw(err);
   }
   catch(Exception err) {
     throw(err);


@@ -294,11 +322,11 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 }
 
 
 }
 
 

-void GroupBlock::generateComments(QTextStream& out) throw(Exception) {
+void GroupBlock::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) {

   out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
 }
 
   out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
 }
 

-void GroupBlock::generateLibraries(QTextStream& out) throw(Exception) {
+void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) {

 
   out << "library IEEE;" << endl;
   out << "use IEEE.STD_LOGIC_1164.all;" << endl;
 
   out << "library IEEE;" << endl;
   out << "use IEEE.STD_LOGIC_1164.all;" << endl;


@@ -306,11 +334,13 @@ void GroupBlock::generateLibraries(QTextStream& out) throw(Exception) {
 
 }
 
 
 }
 

-void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
+void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {

 
   int i;
 
   int i;

-
-  out << "entity " << name << " is " << endl;
+  QString indent = "";
+  for(i=0;i<indentLevel;i++) {
+    indent += " ";
+  }

 
   QList<BlockParameter*> listGenerics = getGenericParameters();
   QList<AbstractInterface*> listInputs = getInputs();
 
   QList<BlockParameter*> listGenerics = getGenericParameters();
   QList<AbstractInterface*> listInputs = getInputs();


@@ -318,21 +348,21 @@ void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
   QList<AbstractInterface*> listBidirs = getBidirs();
 
   if (!listGenerics.isEmpty()) {
   QList<AbstractInterface*> listBidirs = getBidirs();
 
   if (!listGenerics.isEmpty()) {

-    out << "  generic (" << endl;
+    out << indent << "  generic (" << endl;

     for(i=0;i<listGenerics.size()-1;i++) {
     for(i=0;i<listGenerics.size()-1;i++) {

-      out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+      out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;

     }
     }

-    out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
-    out << "    );" << endl;
+    out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << indent << "    );" << endl;

   }
 
   }
 

-  out << "  port (" << endl;
+  out << indent << "  port (" << endl;

 
   // Generation of the clk & rst signals
 
   // Generation of the clk & rst signals

-  out << "    -- clk/rst" << endl;
+  out << indent << "    -- clk/rst" << endl;

   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {

-      out << "    " << iface->getName() << " : in std_logic;" << endl;
+      out << indent << "    " << iface->getName() << " : in std_logic;" << endl;

     }
   }
 
     }
   }
 


@@ -348,68 +378,339 @@ void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- input data ports" << endl;
+        out << indent << "    -- input data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {

-        out << "    -- input control ports" << endl;
+        out << indent << "    -- input control ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- output data ports" << endl;
+        out << indent << "    -- output data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {

-        out << "    -- output control ports" << endl;
+        out << indent << "    -- output control ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- bidirs data ports" << endl;
+        out << indent << "    -- bidirs data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
     }
   }

-  out << "    );" << endl << endl;
-  out << "end " << name << ";" << endl << endl;
-
+  out << indent << "    );" << endl << endl;

 }
 
 }
 

-void GroupBlock::generateArchitecture(QTextStream& out) throw(Exception) {
+void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {
+
+  int i;
+
+  out << "architecture rtl of " << name << " is " << endl << endl;
+
+  // generate type for delays, if needed.
+  QList<int> modWidth;
+  foreach(AbstractBlock* block, blocks) {
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        ConnectedInterface* connIface = AI_TO_CON(connCtlIface->getAssociatedIface());
+        int w = connIface->getWidth();
+        if (w == -1) throw(Exception(INVALID_VALUE));
+        if (!modWidth.contains(w)) {
+          modWidth.append(w);
+        }
+      }
+    }
+  }
+  if (modWidth.size() > 0) {
+
+    out << "  -- types for modified inputs" << endl;
+    out << "  type vector_of_std_logic is array (natural range <>) of std_logic;" << endl;
+    foreach(int w, modWidth) {
+      QString mw = "";
+      mw.setNum(w);
+      QString mwm1 = "";
+      mwm1.setNum(w-1);
+      out << "  type vector_of_std_logic_vector"<< mw << " is array (natural range <>) of std_logic_vector(" << mwm1 << " downto 0);" << endl;
+    }
+    out << endl;
+  }
+
+
+  // generate the components
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      block->generateComponent(out,false);
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+  }
+
+  out << endl;
+  // generate signals
+  out << "  ----------------------------" << endl;
+  out << "  --  SIGNALS" << endl;
+  out << "  ----------------------------" << endl << endl;
+
+  // signals to synchronize inputs
+  out << "  -- signals to synchronize inputs" << endl;
+  foreach(AbstractInterface* iface, getInputs()) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      QString name = iface->toVHDL(AbstractInterface::Signal,0);
+      name.replace(" : ","_sync : ");
+      out << "  signal " << name<< endl;
+    }
+  }
+  out << endl;
+
+  // "normal" signals
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  -- signals from output ports of " << block->getName() << endl;
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      foreach(AbstractInterface* iface, listOutputs) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+        }
+        else if (block->getName() == "clkrstgen") {
+          if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
+            out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+  // signal for modifiers
+  foreach(AbstractBlock* block, blocks) {
+    bool hasModif = false;
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        hasModif = true;
+        break;
+      }
+    }
+    if (hasModif) {
+      try {
+        out << "  -- signals for modified input ports of " << block->getName() << endl;
+        foreach(AbstractInterface* iface, listCtlInputs) {
+          ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+          AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+          if (modifier != NULL) {
+            out << modifier->toVHDL(AbstractInputModifier::Signal,0) << endl;
+          }
+        }
+      }
+      catch(Exception e) {
+        throw(e);
+      }
+      out << endl;
+    }
+  }
+
+  out << "begin" << endl;
+
+  // generate signals that goes to the output ports
+
+  out << "  -- connections to output ports of " << name << endl;
+  QList<AbstractInterface*> listOutputs = getOutputs();
+  foreach(AbstractInterface* iface, listOutputs) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      ConnectedInterface* fromIface = connIface->getConnectedFrom();
+      out << "  " << connIface->getName() << " <= " << fromIface->toVHDL(AbstractInterface::Instance,0) << ";" << endl;
+    }
+  }
+
+  out << endl;
+
+
+
+  // generate instances
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  " << block->getName() << "_1 : " << block->getName() << endl;
+
+      QList<BlockParameter*> listGenerics = block->getGenericParameters();
+      QList<AbstractInterface*> listInputs = block->getInputs();
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      QList<AbstractInterface*> listBidirs = block->getBidirs();

 
 

+      if (!listGenerics.isEmpty()) {
+        out << "    generic map (" << endl;
+        for(i=0;i<listGenerics.size()-1;i++) {
+          out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance, BlockParameter::NoComma) << "," << endl;
+        }
+        out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance,BlockParameter::NoComma) << endl;
+        out << "    )" << endl;
+      }
+
+      out << "    port map (" << endl;
+      QString portMap = "";
+
+      for(i=0;i<listInputs.size();i++) {
+        ConnectedInterface* connIface = AI_TO_CON(listInputs.at(i));
+        ConnectedInterface* fromIface = connIface->getConnectedFrom();
+
+        if (fromIface->isFunctionalInterface()) {
+          portMap += "      " + connIface->getName() + " => ";
+          bool hasMod = false;
+          if (connIface->getPurpose() == AbstractInterface::Data) {
+            ConnectedInterface* connCtlIface = AI_TO_CON(connIface->getAssociatedIface());
+            if ((connCtlIface != NULL) && (connCtlIface->getInputModifier() != NULL)) {
+              hasMod = true;
+            }
+          }
+          else if (connIface->getPurpose() == AbstractInterface::Control) {
+            if (connIface->getInputModifier() != NULL) {
+              hasMod = true;
+            }
+          }
+          if (hasMod) {
+            portMap += connIface->getOwner()->getName()+"_"+connIface->getName()+"_mod,\n";
+          }
+          else {
+            portMap += fromIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+          }
+        }
+        else if (fromIface->isGroupInterface()) {
+          if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+          }
+          else {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+          }
+        }
+      }
+      if (listOutputs.size()>0) {
+        for(i=0;i<listOutputs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listOutputs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+        }
+      }
+      if (listBidirs.size()>0) {
+        for(i=0;i<listBidirs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listBidirs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+        }
+      }
+      portMap.chop(2);
+      out << portMap << endl;
+
+
+      out << "    );" << endl;
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+  // generate input modifiers
+  foreach(AbstractBlock* block, blocks) {
+
+    foreach(AbstractInterface* iface, block->getControlInputs()) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      // check if it is connected
+      if (connIface->getConnectedFrom() == NULL) {
+        throw(Exception(IFACE_NOT_CONNECTED,this));
+      }
+      AbstractInputModifier* modifier = connIface->getInputModifier();
+      if (modifier != NULL) {
+        try {
+          out << modifier->toVHDL(AbstractInputModifier::Architecture,0) << endl;
+        }
+        catch(Exception e) {
+          throw(e);
+        }
+      }
+    }
+  }
+
+  if (topGroup) {
+    // generate input sync process
+    out << "  -- process to synchronize inputs of top group" << endl;
+    out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+    out << "  begin" << endl;
+    out << "    if from_clkrstgen_reset = '1' then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+        }
+      }
+    }
+    out << "    elsif rising_edge(from_clkrstgen_clk) then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+      }
+    }
+    out << "    end if;" << endl;
+    out << "  end process sync_inputs;" << endl;
+
+    out << endl;
+  }
+
+  out << "end architecture rtl;" << endl;
+}
+
+void GroupBlock::generateController(QTextStream &out) throw(Exception) {
+  

 }
 
 }