finished VHDL gen

[blast.git] / AbstractBlock.cpp

diff --git a/AbstractBlock.cpp b/AbstractBlock.cpp
index 336b677a10aeb7f3b75ab64967af1e283181d85c..c1c3c38df0d9d7ab3f6e80af49070ff7121bc648 100644 (file)
--- a/AbstractBlock.cpp
+++ b/AbstractBlock.cpp
@@ -59,10 +59,12 @@ bool AbstractBlock::isSourceBlock() {
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r

+ * By the way, blokcs that have no data input/output\r
+ * (like clkrstgen) are not generators !\r

  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r
  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r

-  \r
+  if (getDataOutputs().size() == 0) return false;\r

   return true;\r
 }\r
 \r
   return true;\r
 }\r
 \r


@@ -247,7 +249,7 @@ void AbstractBlock::connectClkReset() throw(Exception) {
 \r
   GroupBlock* parentBlock = AB_TO_GRP(parent);\r
 \r
 \r
   GroupBlock* parentBlock = AB_TO_GRP(parent);\r
 \r

-  cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r
+\r

 \r
   QList<AbstractInterface* > lstClk = getInterfaces(AbstractInterface::Input,AbstractInterface::Clock);\r
   QList<AbstractInterface* > lstRst = getInterfaces(AbstractInterface::Input,AbstractInterface::Reset);\r
 \r
   QList<AbstractInterface* > lstClk = getInterfaces(AbstractInterface::Input,AbstractInterface::Clock);\r
   QList<AbstractInterface* > lstRst = getInterfaces(AbstractInterface::Input,AbstractInterface::Reset);\r


@@ -271,10 +273,12 @@ void AbstractBlock::connectClkReset() throw(Exception) {
       fromClk = AI_TO_CON(clkrstgen->getIfaceFromName("clk"));\r
       fromRst = AI_TO_CON(clkrstgen->getIfaceFromName("reset"));\r
     }\r
       fromClk = AI_TO_CON(clkrstgen->getIfaceFromName("clk"));\r
       fromRst = AI_TO_CON(clkrstgen->getIfaceFromName("reset"));\r
     }\r

+    cout << "connecting clk/rst for " << qPrintable(name) << " to clkrstgen" << endl;\r

   }\r
   else {\r
     fromClk = AI_TO_CON(parentBlock->getIfaceFromName("clk"));\r
     fromRst = AI_TO_CON(parentBlock->getIfaceFromName("reset"));\r
   }\r
   else {\r
     fromClk = AI_TO_CON(parentBlock->getIfaceFromName("clk"));\r
     fromRst = AI_TO_CON(parentBlock->getIfaceFromName("reset"));\r

+    cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r

   }\r
   if ((fromClk == NULL) || (fromRst == NULL)) {\r
     throw(Exception(IFACE_GROUP_NOCLKRST,parentBlock));\r
   }\r
   if ((fromClk == NULL) || (fromRst == NULL)) {\r
     throw(Exception(IFACE_GROUP_NOCLKRST,parentBlock));\r


@@ -282,10 +286,33 @@ void AbstractBlock::connectClkReset() throw(Exception) {
   else {\r
     fromClk->connectTo(toClk);\r
     fromRst->connectTo(toRst);\r
   else {\r
     fromClk->connectTo(toClk);\r
     fromRst->connectTo(toRst);\r

+    cout << "connection done between " << qPrintable(toClk->getConnectedFrom()->getOwner()->getName()) << "/" << qPrintable(toClk->getConnectedFrom()->getName());\r
+    cout << " and " << qPrintable(toClk->getOwner()->getName()) << "/" << qPrintable(toClk->getName()) << endl;\r

   }\r
   }\r

+}\r

 \r
 \r

+void AbstractBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r

 \r
 \r

+  out << "entity " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 0, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "end entity " << name << ";" << endl << endl;\r

 }\r
 \r
 }\r
 \r

+void AbstractBlock::generateComponent(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "  component " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 2, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "  end component; " << endl << endl;\r
+}\r

 \r
 \r
 \r
 \r