started VHDL generation of GroupBlock

[blast.git] / AbstractBlock.cpp

diff --git a/AbstractBlock.cpp b/AbstractBlock.cpp
index 336b677a10aeb7f3b75ab64967af1e283181d85c..3bb808ead3a61d5491e659821b8e426424e2ae3c 100644 (file)
--- a/AbstractBlock.cpp
+++ b/AbstractBlock.cpp
@@ -59,10 +59,12 @@ bool AbstractBlock::isSourceBlock() {
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r

+ * By the way, blokcs that have no data input/output\r
+ * (like clkrstgen) are not generators !\r

  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r
  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r

-  \r
+  if (getDataOutputs().size() == 0) return false;\r

   return true;\r
 }\r
 \r
   return true;\r
 }\r
 \r


@@ -283,9 +285,30 @@ void AbstractBlock::connectClkReset() throw(Exception) {
     fromClk->connectTo(toClk);\r
     fromRst->connectTo(toRst);\r
   }\r
     fromClk->connectTo(toClk);\r
     fromRst->connectTo(toRst);\r
   }\r

+}\r

 \r
 \r

+void AbstractBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r

 \r
 \r

+  out << "entity " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 0, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "end entity " << name << ";" << endl << endl;\r

 }\r
 \r
 }\r
 \r

+void AbstractBlock::generateComponent(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "  component " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 2, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "  end component " << endl << endl;\r
+}\r

 \r
 \r
 \r
 \r