added clk/rst link when creating a block

[blast.git] / AbstractBlock.h

diff --git a/AbstractBlock.h b/AbstractBlock.h
index c8aa0235dd989cb85708eedaad66bbf5a5b9fd70..fe3f90e392c67c511d86d7060ba07d7eb62b18fe 100644 (file)
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -4,7 +4,9 @@
 #include <iostream>\r
 \r
 #include <QtCore>\r
+#include <QtXml>\r
 \r
+#include "AbstractInterface.h"\r
 class AbstractInterface;\r
 class BlockParameter;\r
 \r
@@ -19,8 +21,10 @@ class AbstractBlock {
 \r
 public:  \r
       \r
+  enum BlockVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Architecture = 3 }; // NB : 3 is when creating an instance of the block that owns this iface\r
+\r
   AbstractBlock();\r
-  AbstractBlock(const QString& _name);\r
+  //AbstractBlock(const QString& _name);\r
   virtual ~AbstractBlock();\r
 \r
   // getters\r
@@ -29,20 +33,21 @@ public:
   inline QList<BlockParameter *> getParameters() { return params; }\r
   inline QList<AbstractInterface*> getInputs() { return inputs; }\r
   inline QList<AbstractInterface*> getOutputs() { return outputs; }\r
-  inline QList<AbstractInterface*> getBidirs() { return bidirs; }\r
+  inline QList<AbstractInterface*> getBidirs() { return bidirs; }  \r
   QList<BlockParameter *> getUserParameters();\r
   QList<BlockParameter *> getGenericParameters();\r
   QList<BlockParameter *> getPortParameters();\r
   QList<BlockParameter *> getWishboneParameters();\r
   inline AbstractBlock* getParent() { return parent; }\r
-  inline QList<int> getProductionCounter() { return productionCounter; }\r
-  inline int getDelta() { return delta; }\r
+  inline bool getPatternComputed() { return patternComputed; }\r
+  inline int getTraversalLevel() { return traversalLevel; }\r
   \r
   // setters\r
   void setName(const QString& str);\r
   virtual void setParent(AbstractBlock* _parent);\r
-  inline void setProductionCounter(QList<int> pattern) { productionCounter = pattern; }\r
-  inline void setDelta(int _delta) { delta = _delta; }\r
+  inline void setPatternComputed(bool state) { patternComputed = state; }\r
+  inline void resetTraversalLevel() { traversalLevel = -1; }\r
+  inline void setTraversalLevel(int level) { traversalLevel = level; }\r
 \r
   // testers\r
   virtual bool isReferenceBlock();\r
@@ -54,6 +59,19 @@ public:
   bool isWBConfigurable();\r
 \r
   // others\r
+\r
+  /*!\r
+   * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces\r
+   * \param idBlockClk is the id of the clock interface (there may be severals)\r
+   * \param idGen is the id of the clkrstgen block\r
+  */\r
+  void connectClock(QString clkName, int idGen = 0) throw(Exception);\r
+  void connectReset(QString rstName, int idGen = 0) throw(Exception);\r
+  virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation\r
+  virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code\r
+  void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference\r
+  void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference\r
+\r
   virtual void parametersValidation(QList<AbstractBlock*>* checkedBlocks, QList<AbstractBlock*>* blocksToConfigure) = 0; // ugly but usefull   \r
 \r
   void addParameter(BlockParameter *param);\r
@@ -62,15 +80,18 @@ public:
   void removeAllInterfaces();\r
   void defineBlockParam(BlockParameter *param);\r
 \r
-  QList<AbstractInterface *> getInterfaces(); //! return all interfaces\r
+  QList<AbstractInterface *> getInterfaces(int direction = AbstractInterface::AnyDirection, int purpose = AbstractInterface::AnyPurpose);\r
   QList<AbstractInterface *> getDataInputs(); //! return all inputs of type data\r
+  QList<AbstractInterface *> getDataOutputs(); //! return all inputs of type data\r
   QList<AbstractInterface *> getControlInputs(); //! return all inputs of type control\r
   QList<AbstractInterface *> getControlOutputs(); //! return all outputs of type control\r
   AbstractInterface* getIfaceFromName(QString name);\r
   BlockParameter* getParameterFromName(QString name);\r
 \r
   // patterns\r
-  virtual void computeOutputPattern(int nbExec = -1) = 0;\r
+  virtual void checkInputPatternCompatibility() throw(Exception) = 0;\r
+  virtual void computeOutputPattern(int nbExec = -1) throw(Exception) = 0;\r
+  virtual void computeAdmittanceDelays() throw(Exception) = 0;\r
   \r
 protected:\r
 \r
@@ -87,12 +108,19 @@ protected:
   \r
   // others\r
   \r
-  // patterns\r
-  QList<int> productionCounter; //! only usefull for output interfaces\r
-  int delta;\r
+  // patterns  \r
+  bool patternComputed;\r
+  int traversalLevel; // the level (0, 1, ...) during the traversal of the graph\r
   \r
   // NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents\r
   AbstractBlock* parent;\r
+\r
+  virtual void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) = 0; // generates comments from <comments> element\r
+  virtual void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) = 0; // generates libraries from <libraries> element  \r
+  virtual void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) = 0; // generate the architecture using <architecture> element\r
+  virtual void generateController(QTextStream& out) throw(Exception) = 0; // generate the wishbone controller of the block\r
+  virtual void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception) = 0; // generate the entity/compo body using reference\r
+\r
 };\r
 \r
 #endif // __ABSTRACTBLOCK_H__\r