start to include clkdomain converters

[blast.git] / lib / implementations / rgb3sx8_to_ycbcr_3DSP_impl.xml

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index e9415791a2448b527085f8b89fe09401f9a352d2..055ec26f337e042fd294bb38ef4a4386201d2692 100644 (file)
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -33,7 +33,6 @@ signal do_sum_cr : std_logic;
 signal do_sum_cr_dly : std_logic;
 signal do_sum_cb : std_logic;
 signal do_sum_cb_dly : std_logic;
 signal do_sum_cr_dly : std_logic;
 signal do_sum_cb : std_logic;
 signal do_sum_cb_dly : std_logic;

-signal do_out : std_logic;

 signal do_out_cr : std_logic;
 signal do_out_cb : std_logic;
 signal do_out_y : std_logic;
 signal do_out_cr : std_logic;
 signal do_out_cb : std_logic;
 signal do_out_y : std_logic;


@@ -69,8 +68,6 @@ signal a_cb : std_logic_vector(17 downto 0);
 signal b_cb : std_logic_vector(17 downto 0);
 signal s_cb : std_logic_vector(47 downto 0);
 
 signal b_cb : std_logic_vector(17 downto 0);
 signal s_cb : std_logic_vector(47 downto 0);
 

-signal compo_out : std_logic_vector(7 downto 0);
-

 begin
 
 y_multiplier : mult_accum
 begin
 
 y_multiplier : mult_accum


@@ -156,7 +153,8 @@ end process multy_process;
 sumy_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
 sumy_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then

-bypass_y <= '0';
+bypass_y <= '1';
+do_sum_y_dly <= '0';

 y <= to_signed(0, 9);
 y_dly1 <= to_signed(0, 9);
 y_dly2 <= to_signed(0, 9);
 y <= to_signed(0, 9);
 y_dly1 <= to_signed(0, 9);
 y_dly2 <= to_signed(0, 9);


@@ -215,7 +213,8 @@ end process multcb_process;
 sumcb_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
 sumcb_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then

-bypass_cb <= '0';
+bypass_cb <= '1';
+do_sum_cb_dly <= '0';

 cb <= to_signed(0, 9);
 cb_dly1 <= to_signed(0, 9);
 elsif rising_edge(@{clk}) then
 cb <= to_signed(0, 9);
 cb_dly1 <= to_signed(0, 9);
 elsif rising_edge(@{clk}) then


@@ -271,7 +270,8 @@ end process multcr_process;
 sumcr_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
 sumcr_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then

-bypass_cr <= '0';
+bypass_cr <= '1';
+do_sum_cr_dly <= '0';

 cr <= to_signed(0, 9);
 do_out_cr <= '0';
 
 cr <= to_signed(0, 9);
 do_out_cr <= '0';