finalized analysis with clkconvert + started testbench gen.

[blast.git] / lib / implementations / rgb3sx8_to_ycbcr_3DSP_impl.xml

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index e9415791a2448b527085f8b89fe09401f9a352d2..5ce24a63fb650097ff97ef0c77e4945082b248b7 100644 (file)
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -2,10 +2,10 @@
 <block_impl ref_name="rgb3sx8_to_ycbcr_3DSP.xml" ref_md5="">
   <comments>
     <author lastname="" mail="" firstname=""/>
-    <date creation="2018-01-10"/>
-    <related_files list=""/>
-    <description>fez</description>
-    <notes>fez</notes>
+    <log creation="2018-05-02">
+    </log>
+    <notes>
+    </notes>    
   </comments>
   <libraries>
     <library name="ieee">
@@ -33,7 +33,6 @@ signal do_sum_cr : std_logic;
 signal do_sum_cr_dly : std_logic;
 signal do_sum_cb : std_logic;
 signal do_sum_cb_dly : std_logic;
-signal do_out : std_logic;
 signal do_out_cr : std_logic;
 signal do_out_cb : std_logic;
 signal do_out_y : std_logic;
@@ -69,8 +68,6 @@ signal a_cb : std_logic_vector(17 downto 0);
 signal b_cb : std_logic_vector(17 downto 0);
 signal s_cb : std_logic_vector(47 downto 0);
 
-signal compo_out : std_logic_vector(7 downto 0);
-
 begin
 
 y_multiplier : mult_accum
@@ -156,7 +153,8 @@ end process multy_process;
 sumy_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_y &lt;= '0';
+bypass_y &lt;= '1';
+do_sum_y_dly &lt;= '0';
 y &lt;= to_signed(0, 9);
 y_dly1 &lt;= to_signed(0, 9);
 y_dly2 &lt;= to_signed(0, 9);
@@ -215,7 +213,8 @@ end process multcb_process;
 sumcb_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cb &lt;= '0';
+bypass_cb &lt;= '1';
+do_sum_cb_dly &lt;= '0';
 cb &lt;= to_signed(0, 9);
 cb_dly1 &lt;= to_signed(0, 9);
 elsif rising_edge(@{clk}) then
@@ -271,7 +270,8 @@ end process multcr_process;
 sumcr_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cr &lt;= '0';
+bypass_cr &lt;= '1';
+do_sum_cr_dly &lt;= '0';
 cr &lt;= to_signed(0, 9);
 do_out_cr &lt;= '0';