+\r
+void FunctionalBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {\r
+\r
+ int i=0;\r
+ QString indent = "";\r
+ for(i=0;i<indentLevel;i++) {\r
+ indent += " ";\r
+ }\r
+ \r
+ //QList<BlockParameter*> listParams = reference->getParameters();\r
+ QList<AbstractInterface*> listInputs = getInputs();\r
+ QList<AbstractInterface*> listOutputs = getOutputs();\r
+ QList<AbstractInterface*> listBidirs = getBidirs(); \r
+\r
+ // Generation of the generics\r
+ QList<BlockParameter*> listGenerics = getGenericParameters();\r
+ if ((!listGenerics.isEmpty()) || (hasController)) {\r
+ out << indent << " generic (" << endl;\r
+ if (hasController) {\r
+ out << indent << " wb_data_width : integer = 16;" << endl;\r
+ out << indent << " wb_addr_width : integer = 12";\r
+ if (!listGenerics.isEmpty()) out << indent << ";";\r
+ out << endl;\r
+ }\r
+ for(i=0;i<listGenerics.size()-1;i++) {\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+\r
+ out << indent << " );" << endl;\r
+ }\r
+\r
+ out << indent << " port (" << endl;\r
+\r
+ QString ports = "";\r
+ QTextStream outPorts(&ports);\r
+\r
+ // Generation of the clk & rst signals\r
+ outPorts << indent << " -- clk/rst" << endl;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ outPorts << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ }\r
+ }\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ outPorts << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
+ }\r
+ }\r
+\r
+ if (hasController) {\r
+ // Generation of the wishbone signals\r
+ outPorts << indent << " -- registers r/w via wishbone" << endl;\r
+ QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
+ for(i=0;i<listWB.size()-1;i++) {\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ }\r
+\r
+ // Generation of the data/control signals\r
+\r
+ QList<AbstractInterface*> listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::InOut, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- bidirs data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+\r
+ ports.chop(2);\r
+ ports += "\n";\r
+ out << ports;\r
+ out << indent << " );" << endl << endl;\r