started VHDL generation of GroupBlock

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 6950b30fbdae11113e9237cad9b66e17e946be87..9a8bb0f857df75dd5843ad5069cc80aa27f852fb 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -5,6 +5,7 @@
 #include "GroupInterface.h"
 #include "string.h"
 #include <sstream>
 #include "GroupInterface.h"
 #include "string.h"
 #include <sstream>

+#include "Parameters.h"

 
 int GroupBlock::counter = 1;
 
 
 int GroupBlock::counter = 1;
 


@@ -31,20 +32,21 @@ GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) :  AbstractBlock()
     rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset);
     addInterface(clk);
     addInterface(rst);
     rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset);
     addInterface(clk);
     addInterface(rst);

-    // creating clkrstgen block : done in Dispatcher since this has no access to library
+    // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library

   }
   parent = _parent;
   }
   parent = _parent;

+

   if (_parent != NULL) {
   if (_parent != NULL) {

-    // adding this to the child blocks of parent    
-    _parent->addBlock(this);
-    // connect clk/rst ifaces to parent clk/rst or to clkrstgen if parent is top group
-    if (_parent->isTop()) {
-      
+    try {
+      connectClkReset();

     }
     }

-    else {
-      
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);

     }
   }
     }
   }

+

 }
 
 GroupBlock::~GroupBlock() {
 }
 
 GroupBlock::~GroupBlock() {


@@ -168,20 +170,22 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
       if (block->getControlOutputs().size() > 0) addIt = true;
     }
     else {
       if (block->getControlOutputs().size() > 0) addIt = true;
     }
     else {

-      // if the block has all its connected inputs that are connected to an intput of the group, add it too
-      addIt = true;
-      foreach(AbstractInterface* iface, block->getControlInputs()) {
-        //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
-        ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
-        //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
-        
-        if (connFrom == NULL) {
-          addIt = false;
-          break;
-        }
-        else if (connFrom->getOwner() != this) {
-          addIt = false;
-          break;
+      // if the block has all its connected control inputs that are connected to an intput of the group, add it too
+      if (block->getControlInputs().size() > 0) {
+        addIt = true;
+        foreach(AbstractInterface* iface, block->getControlInputs()) {
+          //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+          ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+          //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+          if (connFrom == NULL) {
+            addIt = false;
+            break;
+          }
+          else if (connFrom->getOwner() != this) {
+            addIt = false;
+            break;
+          }

         }
       }
     }
         }
       }
     }


@@ -268,7 +272,7 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
   QString coreFile = "";
 
   coreFile = path;
   QString coreFile = "";
 
   coreFile = path;

-  coreFile.append(normalizeName(name));
+  coreFile.append(Parameters::normalizeName(name));

   coreFile.append(".vhd");
 
   QFile vhdlCore(coreFile);
   coreFile.append(".vhd");
 
   QFile vhdlCore(coreFile);


@@ -277,13 +281,15 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
     throw(Exception(VHDLFILE_NOACCESS));
   }
 
     throw(Exception(VHDLFILE_NOACCESS));
   }
 

+  cout << "generate VHDL of block " << qPrintable(name) << " in " << qPrintable(coreFile) << endl;

   QTextStream outCore(&vhdlCore);
 
   QTextStream outCore(&vhdlCore);
 

+  QDomElement dummyElt;

   try {
   try {

-    generateComments(outCore);
-    generateLibraries(outCore);
+    generateComments(outCore,dummyElt,"");
+    generateLibraries(outCore,dummyElt);

     generateEntity(outCore);
     generateEntity(outCore);

-    generateArchitecture(outCore);
+    generateArchitecture(outCore,dummyElt);

   }
   catch(Exception err) {
     throw(err);
   }
   catch(Exception err) {
     throw(err);


@@ -293,11 +299,11 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 }
 
 
 }
 
 

-void GroupBlock::generateComments(QTextStream& out) throw(Exception) {
+void GroupBlock::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) {

   out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
 }
 
   out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
 }
 

-void GroupBlock::generateLibraries(QTextStream& out) throw(Exception) {
+void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) {

 
   out << "library IEEE;" << endl;
   out << "use IEEE.STD_LOGIC_1164.all;" << endl;
 
   out << "library IEEE;" << endl;
   out << "use IEEE.STD_LOGIC_1164.all;" << endl;


@@ -305,11 +311,13 @@ void GroupBlock::generateLibraries(QTextStream& out) throw(Exception) {
 
 }
 
 
 }
 

-void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
+void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {

 
   int i;
 
   int i;

-
-  out << "entity " << name << " is " << endl;
+  QString indent = "";
+  for(i=0;i<indentLevel;i++) {
+    indent += " ";
+  }

 
   QList<BlockParameter*> listGenerics = getGenericParameters();
   QList<AbstractInterface*> listInputs = getInputs();
 
   QList<BlockParameter*> listGenerics = getGenericParameters();
   QList<AbstractInterface*> listInputs = getInputs();


@@ -317,21 +325,21 @@ void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
   QList<AbstractInterface*> listBidirs = getBidirs();
 
   if (!listGenerics.isEmpty()) {
   QList<AbstractInterface*> listBidirs = getBidirs();
 
   if (!listGenerics.isEmpty()) {

-    out << "  generic (" << endl;
+    out << indent << "  generic (" << endl;

     for(i=0;i<listGenerics.size()-1;i++) {
     for(i=0;i<listGenerics.size()-1;i++) {

-      out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+      out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;

     }
     }

-    out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
-    out << "    );" << endl;
+    out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << indent << "    );" << endl;

   }
 
   }
 

-  out << "  port (" << endl;
+  out << indent << "  port (" << endl;

 
   // Generation of the clk & rst signals
 
   // Generation of the clk & rst signals

-  out << "    -- clk/rst" << endl;
+  out << indent << "    -- clk/rst" << endl;

   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {

-      out << "    " << iface->getName() << " : in std_logic;" << endl;
+      out << indent << "    " << iface->getName() << " : in std_logic;" << endl;

     }
   }
 
     }
   }
 


@@ -347,68 +355,126 @@ void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- input data ports" << endl;
+        out << indent << "    -- input data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {

-        out << "    -- input control ports" << endl;
+        out << indent << "    -- input control ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- output data ports" << endl;
+        out << indent << "    -- output data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {

-        out << "    -- output control ports" << endl;
+        out << indent << "    -- output control ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {

-        out << "    -- bidirs data ports" << endl;
+        out << indent << "    -- bidirs data ports" << endl;

         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;

-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;

     }
   }
     }
   }

-  out << "    );" << endl << endl;
-  out << "end " << name << ";" << endl << endl;
-
+  out << indent << "    );" << endl << endl;

 }
 
 }
 

-void GroupBlock::generateArchitecture(QTextStream& out) throw(Exception) {
+void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {

 
 

+  int i;
+
+  out << "architecture rtl of " << name << " is " << endl << endl;
+
+  // generate the components
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      block->generateComponent(out,false);
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+  }
+
+  out << endl;
+  // generate signals
+  out << "  ----------------------------" << endl;
+  out << "    SIGNALS" << endl;
+  out << "  ----------------------------" << endl << endl;
+
+  out << "  -- signals from input ports of " << name << endl;
+  QList<AbstractInterface*> listInputs = getInputs();
+  foreach(AbstractInterface* iface, listInputs) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      QString prefixName = name+"_"+iface->getName()+"_TO_";
+      foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
+        QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
+        out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+      }
+    }
+  }
+  out << endl;
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  -- signals from output ports of " << block->getName() << endl;
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      foreach(AbstractInterface* iface, listOutputs) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          ConnectedInterface* connIface = AI_TO_CON(iface);
+          QString prefixName = block->getName()+"_"+iface->getName()+"_TO_";
+          foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
+            QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
+            out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+
+  out << "end architecture rtl;" << endl;
+}
+
+void GroupBlock::generateController(QTextStream &out) throw(Exception) {
+  

 }
 
 }