nearly finished GroupBlock VHDL gen

[blast.git] / AbstractBlock.h

diff --git a/AbstractBlock.h b/AbstractBlock.h
index 19209b773bad2081e10be79bbd64aadfb16769f2..5f2acb563b8b4a33f30865d7b8606d311683b841 100644 (file)
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -4,7 +4,9 @@
 #include <iostream>\r
 \r
 #include <QtCore>\r
+#include <QtXml>\r
 \r
+#include "AbstractInterface.h"\r
 class AbstractInterface;\r
 class BlockParameter;\r
 \r
@@ -18,9 +20,11 @@ using namespace Qt;
 class AbstractBlock {\r
 \r
 public:  \r
+      \r
+  enum BlockVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Architecture = 3 }; // NB : 3 is when creating an instance of the block that owns this iface\r
 \r
   AbstractBlock();\r
-  AbstractBlock(const QString& _name);\r
+  //AbstractBlock(const QString& _name);\r
   virtual ~AbstractBlock();\r
 \r
   // getters\r
@@ -29,34 +33,59 @@ public:
   inline QList<BlockParameter *> getParameters() { return params; }\r
   inline QList<AbstractInterface*> getInputs() { return inputs; }\r
   inline QList<AbstractInterface*> getOutputs() { return outputs; }\r
-  inline QList<AbstractInterface*> getBidirs() { return bidirs; }\r
+  inline QList<AbstractInterface*> getBidirs() { return bidirs; }  \r
   QList<BlockParameter *> getUserParameters();\r
   QList<BlockParameter *> getGenericParameters();\r
   QList<BlockParameter *> getPortParameters();\r
   QList<BlockParameter *> getWishboneParameters();\r
   inline AbstractBlock* getParent() { return parent; }\r
+  inline bool getPatternComputed() { return patternComputed; }\r
+  inline int getTraversalLevel() { return traversalLevel; }\r
+  \r
   // setters\r
   void setName(const QString& str);\r
   virtual void setParent(AbstractBlock* _parent);\r
+  inline void setPatternComputed(bool state) { patternComputed = state; }\r
+  inline void resetTraversalLevel() { traversalLevel = -1; }\r
+  inline void setTraversalLevel(int level) { traversalLevel = level; }\r
 \r
   // testers\r
   virtual bool isReferenceBlock();\r
   virtual bool isFunctionalBlock();\r
   virtual bool isGroupBlock();\r
+  virtual bool isSourceBlock(); //! a source block is outside the top group and simulates a peripheral (NB: this is also a generator)\r
+  virtual bool isTopGroupBlock();\r
+  bool isGeneratorBlock(); //! a generator block has no data inputs and thus executes infinitely\r
   bool isWBConfigurable();\r
 \r
   // others\r
+  void connectClkReset() throw(Exception);  \r
+\r
+  virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code\r
+  void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference\r
+  void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference\r
+\r
   virtual void parametersValidation(QList<AbstractBlock*>* checkedBlocks, QList<AbstractBlock*>* blocksToConfigure) = 0; // ugly but usefull   \r
 \r
   void addParameter(BlockParameter *param);\r
   void addInterface(AbstractInterface *inter);\r
   void removeInterface(AbstractInterface *inter);\r
+  void removeAllInterfaces();\r
   void defineBlockParam(BlockParameter *param);\r
 \r
-  QList<AbstractInterface *> getInterfaces();\r
+  QList<AbstractInterface *> getInterfaces(int direction = AbstractInterface::AnyDirection, int purpose = AbstractInterface::AnyPurpose);\r
+  QList<AbstractInterface *> getDataInputs(); //! return all inputs of type data\r
+  QList<AbstractInterface *> getDataOutputs(); //! return all inputs of type data\r
+  QList<AbstractInterface *> getControlInputs(); //! return all inputs of type control\r
+  QList<AbstractInterface *> getControlOutputs(); //! return all outputs of type control\r
   AbstractInterface* getIfaceFromName(QString name);\r
   BlockParameter* getParameterFromName(QString name);\r
 \r
+  // patterns\r
+  virtual void checkInputPatternCompatibility() throw(Exception) = 0;\r
+  virtual void computeOutputPattern(int nbExec = -1) throw(Exception) = 0;\r
+  virtual void computeAdmittanceDelays() throw(Exception) = 0;\r
+  \r
 protected:\r
 \r
 \r
@@ -69,11 +98,22 @@ protected:
   QList<AbstractInterface*> inputs;\r
   QList<AbstractInterface*> outputs;\r
   QList<AbstractInterface*> bidirs;\r
-\r
+  \r
   // others\r
-\r
-  // NB: only GroupBlock and FunctionalBlock have a real parent\r
+  \r
+  // patterns  \r
+  bool patternComputed;\r
+  int traversalLevel; // the level (0, 1, ...) during the traversal of the graph\r
+  \r
+  // NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents\r
   AbstractBlock* parent;\r
+\r
+  virtual void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) = 0; // generates comments from <comments> element\r
+  virtual void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) = 0; // generates libraries from <libraries> element  \r
+  virtual void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) = 0; // generate the architecture using <architecture> element\r
+  virtual void generateController(QTextStream& out) throw(Exception) = 0; // generate the wishbone controller of the block\r
+  virtual void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception) = 0; // generate the entity/compo body using reference\r
+\r
 };\r
 \r
 #endif // __ABSTRACTBLOCK_H__\r