X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/015e6979cd7d336f6bbebfbdb7916af3ba23c096..14cd6d834ab531525a51c6a6992583b3e9143e02:/Makefile-isim

diff --git a/Makefile-isim b/Makefile-isim
index c10eb1d..15319a1 100644
--- a/Makefile-isim
+++ b/Makefile-isim
@@ -8,16 +8,16 @@ ISIM_LIB := work
 
 all : project compile 
 
-project : $(PROJECT).prj
+project : $(PROJECT_NAME).prj
 
-compile : $(PROJECT).prj $(VHDL_SRC)
+compile : $(PROJECT_NAME).prj $(VHDL_SRC)
 	tb_name=$$( echo $(TB_SRC) | sed 's,.*/,,' | sed 's,[.].*,,'); \
-	fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)
+	fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT_NAME).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)
 
 view :
 	$(SIMU_EXE) -gui -wdb $(SIMU_EXE).wdb
 
-$(PROJECT).prj :
+$(PROJECT_NAME).prj :
 	if [ -f $@ ]; then rm $@; fi
 	echo "### VHDL sources"
 	for fich in $(VHDL_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done
@@ -28,6 +28,6 @@ $(PROJECT).prj :
 
 clean :
 	rm -f *~
-	rm -f $(PROJECT).prj
+	rm -f $(PROJECT_NAME).prj
 	cd $(SRC_DIR); rm -f *~
 	cd $(TB_DIR); rm -f *~