X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/015e6979cd7d336f6bbebfbdb7916af3ba23c096..8f0bedf735fe2b306c11c3f4a168245a05e37ccd:/FunctionalBlock.cpp?ds=sidebyside

diff --git a/FunctionalBlock.cpp b/FunctionalBlock.cpp
index 1ec0c11..3ea8253 100644
--- a/FunctionalBlock.cpp
+++ b/FunctionalBlock.cpp
@@ -1451,57 +1451,61 @@ void FunctionalBlock::generateLibraries(QTextStream& out, QDomElement &elt) thro
   }
 }
 
-void FunctionalBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {
+
+void FunctionalBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {
 
   int i=0;
+  QString indent = "";
+  for(i=0;i<indentLevel;i++) {
+    indent += " ";
+  }
   
   //QList<BlockParameter*> listParams = reference->getParameters();
   QList<AbstractInterface*> listInputs = getInputs();
   QList<AbstractInterface*> listOutputs = getOutputs();
-  QList<AbstractInterface*> listBidirs = getBidirs();
-  QString typePort, namePort;
-
-  out << "entity " << name << " is" << endl;
-
-
-  /* TODO : rewrite the generation to take into acocunt the new object hierarchy */
+  QList<AbstractInterface*> listBidirs = getBidirs();    
 
   // Generation of the generics
   QList<BlockParameter*> listGenerics = getGenericParameters();
   if ((!listGenerics.isEmpty()) || (hasController)) {
-    out << "  generic (" << endl;
+    out << indent << "  generic (" << endl;
     if (hasController) {
-      out << "    wb_data_width : integer = 16;" << endl;
-      out << "    wb_addr_width : integer = 12";
-      if (!listGenerics.isEmpty()) out << ";";
+      out << indent << "    wb_data_width : integer = 16;" << endl;
+      out << indent << "    wb_addr_width : integer = 12";
+      if (!listGenerics.isEmpty()) out << indent << ";";
       out << endl;
     }
     for(i=0;i<listGenerics.size()-1;i++) {
-      out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+      out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
     }
-    out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
 
-    out << "    );" << endl;
+    out << indent << "    );" << endl;
   }
 
-  out << "  port (" << endl;
+  out << indent << "  port (" << endl;
 
   // Generation of the clk & rst signals
-  out << "    -- clk/rst" << endl;
+  out << indent << "    -- clk/rst" << endl;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
-      out << "    " << iface->getName() << " : in std_logic;" << endl;
+      out << indent << "    " << iface->getName() << " : in std_logic;" << endl;
+    }
+  }
+  foreach(AbstractInterface* iface, listOutputs) {
+    if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
+      out << indent << "    " << iface->getName() << " : out std_logic;" << endl;
     }
   }
 
   if (hasController) {
     // Generation of the wishbone signals
-    out << "    -- registers r/w via wishbone" << endl;
+    out << indent << "    -- registers r/w via wishbone" << endl;
     QList<BlockParameter*> listWB = reference->getWishboneParameters();
     for(i=0;i<listWB.size()-1;i++) {
-      out << "    " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+      out << indent << "    " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
     }
-    out << "    " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << indent << "    " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
   }
 
 
@@ -1517,64 +1521,64 @@ void FunctionalBlock::generateEntity(QTextStream& out, bool hasController) throw
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- input data ports" << endl;
+        out << indent << "    -- input data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
-        out << "    -- input control ports" << endl;
+        out << indent << "    -- input control ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- output data ports" << endl;
+        out << indent << "    -- output data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
-        out << "    -- output control ports" << endl;
+        out << indent << "    -- output control ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- bidirs data ports" << endl;
+        out << indent << "    -- bidirs data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
-  out << "    );" << endl << endl;
-  out << "end " << name << ";" << endl << endl;
+  out << indent << "    );" << endl << endl;
+
 }
 
 void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {