X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/14cd6d834ab531525a51c6a6992583b3e9143e02..6ca6321283b9c93a6df9dcd5216bfa01df9ad24b:/Dispatcher.cpp

diff --git a/Dispatcher.cpp b/Dispatcher.cpp
index b9e09a9..cdf8ee3 100644
--- a/Dispatcher.cpp
+++ b/Dispatcher.cpp
@@ -256,11 +256,18 @@ void Dispatcher::generateVHDL() throw(Exception) {
   }
   out << endl;
   out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
-  out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+  out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl;
+  out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
   out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
 
   paramFile.close();
 
+  QString msg = "VHDL generation completed successfully. Go to ";
+  msg += params->projectPath+" and type the following commands to launch a simulation:\n";
+  msg += "\tmake clean\n";
+  msg += "\tmake\n";
+  msg += "\tmake view\n";
+  QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok);
 
 }