X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/4cf57e6db08da791233d75237f62e74bc88dd427..015e6979cd7d336f6bbebfbdb7916af3ba23c096:/BlockImplementation.cpp?ds=inline diff --git a/BlockImplementation.cpp b/BlockImplementation.cpp index f71297f..23ec8bc 100644 --- a/BlockImplementation.cpp +++ b/BlockImplementation.cpp @@ -15,6 +15,8 @@ BlockImplementation::BlockImplementation(const QString& _xmlFile) { evaluator = new ArithmeticEvaluator; evaluator->setVariableMarkers("@$"); + + noPatterns = true; } BlockImplementation::BlockImplementation(const QString& _xmlFile, const QString &_referenceXml, const QString &_referenceMd5) { @@ -23,6 +25,8 @@ BlockImplementation::BlockImplementation(const QString& _xmlFile, const QString delta = ""; referenceXml = _referenceXml; referenceMd5 = _referenceMd5; + + noPatterns = true; } void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { @@ -38,7 +42,8 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QDomElement eltDelta = patternElt.firstChildElement("delta"); delta = eltDelta.attribute("value","none"); - + if (delta == "none") throw(Exception(IMPLFILE_CORRUPTED)); + QDomElement eltCons = eltDelta.nextSiblingElement("consumption"); QDomNodeList listNodeInput = eltCons.elementsByTagName("input"); @@ -47,7 +52,8 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QDomElement elt = node.toElement(); QString nameStr = elt.attribute("name","none"); if (nameStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); - QString patternStr = elt.attribute("pattern","none"); + QString patternStr = elt.attribute("pattern","none"); + if (patternStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); consumptionPattern.insert(nameStr,patternStr); } @@ -61,6 +67,7 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QString nameStr = elt.attribute("name","none"); if (nameStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); QString patternStr = elt.attribute("pattern","none"); + if (patternStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); productionPattern.insert(nameStr,patternStr); } cout << "patterns summary:" << endl; @@ -70,6 +77,7 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { cout << qPrintable(iterP.key()) << " -> " << qPrintable(iterP.value()) << endl; } cout << "impls patterns read correctly" << endl; + noPatterns = false; } bool BlockImplementation::checkPatterns() { @@ -102,310 +110,6 @@ bool BlockImplementation::checkPatterns() { return true; } -void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &path) throw(Exception) { - - block = _block; - - QFile implFile(xmlFile); - - // reading in into QDomDocument - QDomDocument document("implFile"); - - if (!implFile.open(QIODevice::ReadOnly)) { - throw(Exception(IMPLFILE_NOACCESS)); - } - if (!document.setContent(&implFile)) { - implFile.close(); - throw(Exception(IMPLFILE_NOACCESS)); - } - implFile.close(); - - bool genController = false; - QString coreFile = ""; - QString controllerFile = ""; - - if (reference->isWBConfigurable()) { - genController = true; - controllerFile = path; - controllerFile.append(block->getName()); - controllerFile.append("_ctrl.vhd"); - } - else { - controllerFile = "nofile.vhd"; - } - coreFile = path; - coreFile.append(block->getName()); - coreFile.append(".vhd"); - - QFile vhdlCore(coreFile); - QFile vhdlController(controllerFile); - - if (!vhdlCore.open(QIODevice::WriteOnly)) { - throw(Exception(VHDLFILE_NOACCESS)); - } - - if (genController) { - if (!vhdlController.open(QIODevice::WriteOnly)) { - throw(Exception(VHDLFILE_NOACCESS)); - } - } - QTextStream outCore(&vhdlCore); - QTextStream outController; - if (genController) { - outController.setDevice(&vhdlController); - } - - try { - - - //Get the root element - QDomElement impl = document.documentElement(); - QDomElement eltComments = impl.firstChildElement("comments"); - generateComments(eltComments, coreFile, outCore); - QDomElement eltLibs = eltComments.nextSiblingElement("libraries"); - generateLibraries(eltLibs, outCore); - generateEntity(outCore, genController); - QDomElement eltArch = eltLibs.nextSiblingElement("architecture"); - generateArchitecture(eltArch, outCore); - if (genController) { - generateController(outController); - } - } - catch(Exception err) { - throw(err); - } - - vhdlCore.close(); - vhdlController.close(); -} - -// This function generates the comments part of the VHDL document -void BlockImplementation::generateComments(QDomElement &elt, QString coreFile, QTextStream& out) throw(Exception) { - - for(int i = 0; i < 50; i++) { - out << "--"; - } - out << "\n--\n"; - QString fileName = coreFile; - out << "-- File : " << fileName << "\n"; - out << "--\n"; - QDomElement eltAuthor = elt.firstChildElement("author"); - QString firstName = eltAuthor.attribute("firstname",""); - QString lastName = eltAuthor.attribute("lastname",""); - QString mail = eltAuthor.attribute("mail",""); - out << "-- Author(s) : "<getName(); - //QList listParams = reference->getParameters(); - QList listInputs = block->getInputs(); - QList listOutputs = block->getOutputs(); - QList listBidirs = block->getBidirs(); - QString typePort, namePort; - - out << "entity " << nameEnt << " is\n"; - - - /* TODO : rewrite the generation to take into acocunt the new object hierarchy */ - - // Generation of the generics - QList listGenerics = block->getGenericParameters(); - if ((!listGenerics.isEmpty()) || (hasController)) { - out << " generic (" << endl; - if (hasController) { - out << " wb_data_width : integer = 16;" << endl; - out << " wb_addr_width : integer = 12"; - if (!listGenerics.isEmpty()) out << ";"; - out << endl; - } - for(i=0;itoVHDL(BlockParameter::Entity, 0) << endl; - } - out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; - - out << " );" << endl; - } - - out << " port (" << endl; - - // Generation of the clk & rst signals - out << " -- clk/rst" << endl; - foreach(AbstractInterface* iface, listInputs) { - if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) { - out << " " << iface->getName() << " : in std_logic;" << endl; - } - } - - if (hasController) { - // Generation of the wishbone signals - out << " -- registers r/w via wishbone" << endl; - QList listWB = reference->getWishboneParameters(); - for(i=0;itoVHDL(BlockParameter::Entity, 0) << endl; - } - out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; - } - - - int count = 0; - foreach(AbstractInterface* iface, block->getInterfaces()) { - if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++; - } - // Generation of the data/control signals - - int flag = 0; - bool first = true; - - foreach(AbstractInterface* iface, listInputs) { - if(iface->getPurpose() == AbstractInterface::Data) { - if (first) { - out << " -- input data ports" << endl; - first = false; - } - count--; - if (count == 0) flag = AbstractInterface::NoComma; - out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; - } - } - first = true; - foreach(AbstractInterface* iface, listInputs) { - if(iface->getPurpose() == AbstractInterface::Control) { - if (first) { - out << " -- input control ports" << endl; - first = false; - } - count--; - if (count == 0) flag = AbstractInterface::NoComma; - out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; - } - } - first = true; - foreach(AbstractInterface* iface, listOutputs) { - if(iface->getPurpose() == AbstractInterface::Data) { - if (first) { - out << " -- output data ports" << endl; - first = false; - } - count--; - if (count == 0) flag = AbstractInterface::NoComma; - out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; - } - } - first = true; - foreach(AbstractInterface* iface, listOutputs) { - if(iface->getPurpose() == AbstractInterface::Control) { - if (first) { - out << " -- output control ports" << endl; - first = false; - } - count--; - if (count == 0) flag = AbstractInterface::NoComma; - out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; - } - } - first = true; - foreach(AbstractInterface* iface, listBidirs) { - if(iface->getPurpose() == AbstractInterface::Data) { - if (first) { - out << " -- bidirs data ports" << endl; - first = false; - } - count--; - if (count == 0) flag = AbstractInterface::NoComma; - out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; - } - } - out << " );" << endl << endl; - out << "end " << nameEnt << ";" << endl << endl; -} - -// This function generates the architecture part of the VHDL document -void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) { - - QString expr; - QString code = elt.text(); - cout << qPrintable(code) << endl; - out << "architecture rtl of " << nameEnt << " is" << endl; - - QStringList listLine = code.split("\n"); - for(int i =0; i < listLine.size(); i++) { - QString line = listLine.at(i).simplified(); - - /* - if(listLine.at(i).contains(QRegularExpression("@foreach{"))) { - while(listLine.at(i).compare("@endforeach") != -1) { - expr = expr + listLine.at(i) + '\n'; - i++; - } - expr = expr + listLine.at(i); - out << evalComplex(expr, 1) << '\n'; - } - if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) { - while(listLine.at(i).compare("@endcaseeach") != -1) { - expr = expr + listLine.at(i) + '\n'; - i++; - } - expr = expr + listLine.at(i); - out << evalComplex(expr, 2) << '\n'; - } -*/ - if(line.contains("@{")) { - out << line << endl; - } - } -} - -void BlockImplementation::generateController(QTextStream &out) throw(Exception) { -} - QString BlockImplementation::eval(QString line, QTextStream& out) { QString res, s, begLine, endLine, expr; evaluator->setExpression(line); @@ -628,6 +332,7 @@ QDataStream& operator<<(QDataStream &out, const BlockImplementation &impl) { toWrite << impl.referenceXml; toWrite << impl.referenceMd5; // saving patterns + toWrite << impl.noPatterns; toWrite << impl.delta; toWrite << impl.consumptionPattern; toWrite << impl.productionPattern; @@ -650,6 +355,7 @@ QDataStream& operator>>(QDataStream &in, BlockImplementation &impl) { in >> impl.referenceXml; in >> impl.referenceMd5; // loading patterns + in >> impl.noPatterns; in >> impl.delta; in >> impl.consumptionPattern; in >> impl.productionPattern;