X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/4cf57e6db08da791233d75237f62e74bc88dd427..6e2b3026c6a496e81642c373796bd39dad33d2a6:/GroupBlock.cpp?ds=sidebyside diff --git a/GroupBlock.cpp b/GroupBlock.cpp index b515b54..9a8bb0f 100644 --- a/GroupBlock.cpp +++ b/GroupBlock.cpp @@ -2,27 +2,51 @@ #include "BlockParameterGeneric.h" #include "AbstractInterface.h" #include "ConnectedInterface.h" +#include "GroupInterface.h" #include "string.h" #include +#include "Parameters.h" int GroupBlock::counter = 1; GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() { + GroupInterface* clk = NULL; + GroupInterface* rst = NULL; + // force topGroup to false if this group has a parent if (_parent != NULL) { topGroup = false; name = QString("sub_group")+"_"+QString::number(counter++); + // creating clk/rst interfaces + clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock); + rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset); + addInterface(clk); + addInterface(rst); } else { topGroup = true; name = QString("top_group"); + // creating external clk/rst interfaces + clk = new GroupInterface(this,"ext_clk", AbstractInterface::Input, AbstractInterface::Clock); + rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset); + addInterface(clk); + addInterface(rst); + // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library } parent = _parent; - if (parent != NULL) { - // adding this to the child blocks of parent - AB_TO_GRP(parent)->addBlock(this); + + if (_parent != NULL) { + try { + connectClkReset(); + } + catch(Exception e) { + AbstractBlock* source = (AbstractBlock *)(e.getSource()); + cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl; + throw(e); + } } + } GroupBlock::~GroupBlock() { @@ -146,20 +170,22 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { if (block->getControlOutputs().size() > 0) addIt = true; } else { - // if the block has all its connected inputs that are connected to an intput of the group, add it too - addIt = true; - foreach(AbstractInterface* iface, block->getControlInputs()) { - //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl; - ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); - //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl; - - if (connFrom == NULL) { - addIt = false; - break; - } - else if (connFrom->getOwner() != this) { - addIt = false; - break; + // if the block has all its connected control inputs that are connected to an intput of the group, add it too + if (block->getControlInputs().size() > 0) { + addIt = true; + foreach(AbstractInterface* iface, block->getControlInputs()) { + //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl; + ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); + //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl; + + if (connFrom == NULL) { + addIt = false; + break; + } + else if (connFrom->getOwner() != this) { + addIt = false; + break; + } } } } @@ -239,5 +265,216 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { } setPatternComputed(true); } +} + +void GroupBlock::generateVHDL(const QString& path) throw(Exception) { + + QString coreFile = ""; + + coreFile = path; + coreFile.append(Parameters::normalizeName(name)); + coreFile.append(".vhd"); + + QFile vhdlCore(coreFile); + + if (!vhdlCore.open(QIODevice::WriteOnly)) { + throw(Exception(VHDLFILE_NOACCESS)); + } + + cout << "generate VHDL of block " << qPrintable(name) << " in " << qPrintable(coreFile) << endl; + QTextStream outCore(&vhdlCore); + + QDomElement dummyElt; + try { + generateComments(outCore,dummyElt,""); + generateLibraries(outCore,dummyElt); + generateEntity(outCore); + generateArchitecture(outCore,dummyElt); + } + catch(Exception err) { + throw(err); + } + + vhdlCore.close(); +} + + +void GroupBlock::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) { + out << " -- VHDL generated automatically for " << name << " --" << endl << endl; +} + +void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) { + + out << "library IEEE;" << endl; + out << "use IEEE.STD_LOGIC_1164.all;" << endl; + out << "use IEEE.numeric_std.all;" << endl; + +} + +void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) { + + int i; + QString indent = ""; + for(i=0;i listGenerics = getGenericParameters(); + QList listInputs = getInputs(); + QList listOutputs = getOutputs(); + QList listBidirs = getBidirs(); + + if (!listGenerics.isEmpty()) { + out << indent << " generic (" << endl; + for(i=0;itoVHDL(BlockParameter::Entity, 0) << endl; + } + out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; + out << indent << " );" << endl; + } + + out << indent << " port (" << endl; + + // Generation of the clk & rst signals + out << indent << " -- clk/rst" << endl; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) { + out << indent << " " << iface->getName() << " : in std_logic;" << endl; + } + } + int count = 0; + foreach(AbstractInterface* iface, getInterfaces()) { + if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++; + } + // Generation of the data/control signals + + int flag = 0; + bool first = true; + + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << indent << " -- input data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << indent << " -- input control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << indent << " -- output data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << indent << " -- output control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listBidirs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << indent << " -- bidirs data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + out << indent << " );" << endl << endl; +} + +void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) { + + int i; + + out << "architecture rtl of " << name << " is " << endl << endl; + + // generate the components + foreach(AbstractBlock* block, blocks) { + try { + block->generateComponent(out,false); + } + catch(Exception e) { + throw(e); + } + } + + out << endl; + // generate signals + out << " ----------------------------" << endl; + out << " SIGNALS" << endl; + out << " ----------------------------" << endl << endl; + + out << " -- signals from input ports of " << name << endl; + QList listInputs = getInputs(); + foreach(AbstractInterface* iface, listInputs) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + ConnectedInterface* connIface = AI_TO_CON(iface); + QString prefixName = name+"_"+iface->getName()+"_TO_"; + foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) { + QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName(); + out << " signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl; + } + } + } + out << endl; + foreach(AbstractBlock* block, blocks) { + try { + out << " -- signals from output ports of " << block->getName() << endl; + QList listOutputs = block->getOutputs(); + foreach(AbstractInterface* iface, listOutputs) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + ConnectedInterface* connIface = AI_TO_CON(iface); + QString prefixName = block->getName()+"_"+iface->getName()+"_TO_"; + foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) { + QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName(); + out << " signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl; + } + } + } + } + catch(Exception e) { + throw(e); + } + out << endl; + } + + + out << "end architecture rtl;" << endl; +} + +void GroupBlock::generateController(QTextStream &out) throw(Exception) { + } +