X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/4cf57e6db08da791233d75237f62e74bc88dd427..a7299f808c1906872b76aa62fb6d8276096c4ff5:/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index 3db4b59..055ec26 100644
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -13,7 +13,7 @@
       <package name="numeric_std" use="all"/>
     </library>
   </libraries>
-  <architecture>
+  <architecture comp_list="mult_accum">
 component mult_accum
 port (
 @{clk} : in std_logic;
@@ -33,7 +33,6 @@ signal do_sum_cr : std_logic;
 signal do_sum_cr_dly : std_logic;
 signal do_sum_cb : std_logic;
 signal do_sum_cb_dly : std_logic;
-signal do_out : std_logic;
 signal do_out_cr : std_logic;
 signal do_out_cb : std_logic;
 signal do_out_y : std_logic;
@@ -69,8 +68,6 @@ signal a_cb : std_logic_vector(17 downto 0);
 signal b_cb : std_logic_vector(17 downto 0);
 signal s_cb : std_logic_vector(47 downto 0);
 
-signal compo_out : std_logic_vector(7 downto 0);
-
 begin
 
 y_multiplier : mult_accum
@@ -156,7 +153,8 @@ end process multy_process;
 sumy_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_y &lt;= '0';
+bypass_y &lt;= '1';
+do_sum_y_dly &lt;= '0';
 y &lt;= to_signed(0, 9);
 y_dly1 &lt;= to_signed(0, 9);
 y_dly2 &lt;= to_signed(0, 9);
@@ -215,7 +213,8 @@ end process multcb_process;
 sumcb_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cb &lt;= '0';
+bypass_cb &lt;= '1';
+do_sum_cb_dly &lt;= '0';
 cb &lt;= to_signed(0, 9);
 cb_dly1 &lt;= to_signed(0, 9);
 elsif rising_edge(@{clk}) then
@@ -271,7 +270,8 @@ end process multcr_process;
 sumcr_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cr &lt;= '0';
+bypass_cr &lt;= '1';
+do_sum_cr_dly &lt;= '0';
 cr &lt;= to_signed(0, 9);
 do_out_cr &lt;= '0';
 
@@ -304,8 +304,6 @@ std_logic_vector(cb_dly1(7 downto 0)) when do_out_cb = '1' else
 std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
 (others => '0');
 @{ycbcr_out_enb} &lt;= do_out_y or do_out_cb or do_out_cr;
-
-end rtl;
 </architecture>
   <patterns>
     <delta value="3"/>