X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/56f7c4239666506c59af42885f0bf0141d21a614..8fb3c55ee009a11db5e1c08a4cfb286979412745:/VHDLConverter.cpp

diff --git a/VHDLConverter.cpp b/VHDLConverter.cpp
index 42fff3a..275ceb4 100644
--- a/VHDLConverter.cpp
+++ b/VHDLConverter.cpp
@@ -359,14 +359,18 @@ void VHDLConverter::readPorts(QTextStream &in) throw(Exception) {
 void VHDLConverter::readArchitecture(QTextStream &in) throw(Exception) {
 
   QString line = "";
-  QString endLine = "end "+archName;
+  QString endLine1 = "end "+archName;
+  QString endLine2 = "end architecture "+archName;
+  bool stop = false;
 
-  while (!line.startsWith(endLine)) {
+  while (!stop) {
     line = in.readLine();
     if (!line.isEmpty()) line = line.simplified();
     archLines.append(line);
-  }
-  
+    if ((line.startsWith(endLine1)) || (line.startsWith(endLine2)) ) {
+      stop = true;
+    }
+  }  
 }
 
 // This function opens a VHDL file and get the informations about the entity :
@@ -459,12 +463,12 @@ void VHDLConverter::loadVHDLFile() {
     else {
       widthStr = "std_logic_vector(";
       if (iface->getEndianess() == AbstractInterface::LittleEndian) {
-        widthStr += iface->getWidth();
+        widthStr += iface->getWidthString();
         widthStr += " downto 0)";
       }
       else {
         widthStr += "0 to ";
-        widthStr += iface->getWidth();
+        widthStr += iface->getWidthString();
         widthStr += ")";
       }
     }
@@ -651,7 +655,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement input = doc.createElement("input");
         input.setAttribute("name",iface->getName());
         input.setAttribute("type",iface->getTypeString());
-        input.setAttribute("width",iface->getWidth());
+        input.setAttribute("width",iface->getWidthString());
         input.setAttribute("multiplicity","1");
         input.setAttribute("purpose",iface->getPurposeString());
         input.setAttribute("endian",iface->getEndianessString());
@@ -673,7 +677,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement output = doc.createElement("output");
         output.setAttribute("name",iface->getName());
         output.setAttribute("type",iface->getTypeString());
-        output.setAttribute("width",iface->getWidth());
+        output.setAttribute("width",iface->getWidthString());
         output.setAttribute("multiplicity","1");
         output.setAttribute("purpose",iface->getPurposeString());
         output.setAttribute("endian",iface->getEndianessString());
@@ -695,7 +699,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement bidir = doc.createElement("bidir");
         bidir.setAttribute("name",iface->getName());
         bidir.setAttribute("type",iface->getTypeString());
-        bidir.setAttribute("width",iface->getWidth());
+        bidir.setAttribute("width",iface->getWidthString());
         bidir.setAttribute("multiplicity","1");
         bidir.setAttribute("purpose",iface->getPurposeString());
         bidir.setAttribute("endian",iface->getEndianessString());
@@ -826,11 +830,12 @@ void VHDLConverter::replaceSignalNames(QString& line) {
 void VHDLConverter::updateArchitecture() {
   QRegularExpression rxLT("<=",QRegularExpression::CaseInsensitiveOption);
   QRegularExpression rxGT("=>",QRegularExpression::CaseInsensitiveOption);
-  foreach(QString line, archLines) {
+  for(int i=0;i<archLines.size();i++) {
+    QString line = archLines.at(i);
     replaceSignalNames(line);
-    line.replace(rxLT,"&lt;=");
-    line.replace(rxGT,"=&gt;");
-
+    //line.replace(rxLT,"&lt;=");
+    //line.replace(rxGT,"=&gt;");
+    archLines.replace(i,line);
     cout << qPrintable(line) << endl;
   }
 }