X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/5d4e709cb8d460b2efc083e6e7999f1c3a0eb602..6e2b3026c6a496e81642c373796bd39dad33d2a6:/BlockImplementation.cpp?ds=inline diff --git a/BlockImplementation.cpp b/BlockImplementation.cpp index e6b61ca..23ec8bc 100644 --- a/BlockImplementation.cpp +++ b/BlockImplementation.cpp @@ -15,6 +15,8 @@ BlockImplementation::BlockImplementation(const QString& _xmlFile) { evaluator = new ArithmeticEvaluator; evaluator->setVariableMarkers("@$"); + + noPatterns = true; } BlockImplementation::BlockImplementation(const QString& _xmlFile, const QString &_referenceXml, const QString &_referenceMd5) { @@ -23,6 +25,8 @@ BlockImplementation::BlockImplementation(const QString& _xmlFile, const QString delta = ""; referenceXml = _referenceXml; referenceMd5 = _referenceMd5; + + noPatterns = true; } void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { @@ -38,7 +42,8 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QDomElement eltDelta = patternElt.firstChildElement("delta"); delta = eltDelta.attribute("value","none"); - + if (delta == "none") throw(Exception(IMPLFILE_CORRUPTED)); + QDomElement eltCons = eltDelta.nextSiblingElement("consumption"); QDomNodeList listNodeInput = eltCons.elementsByTagName("input"); @@ -47,305 +52,64 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QDomElement elt = node.toElement(); QString nameStr = elt.attribute("name","none"); if (nameStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); - QString patternStr = elt.attribute("pattern","none"); + QString patternStr = elt.attribute("pattern","none"); + if (patternStr == "none") throw(Exception(IMPLFILE_CORRUPTED)); consumptionPattern.insert(nameStr,patternStr); } QDomElement eltProd = eltCons.nextSiblingElement("production"); + productionCounter = eltProd.attribute("counter","none"); - QDomNodeList listNodeOutput = eltCons.elementsByTagName("output"); + QDomNodeList listNodeOutput = eltProd.elementsByTagName("output"); for(int i=0; i iterP(productionPattern); + while (iterP.hasNext()) { + iterP.next(); + cout << qPrintable(iterP.key()) << " -> " << qPrintable(iterP.value()) << endl; + } cout << "impls patterns read correctly" << endl; + noPatterns = false; } bool BlockImplementation::checkPatterns() { - if (reference == NULL) return false; + + + if (reference == NULL) { + cout << "no ref. while checking patterns of implementation " << endl; + return false; + } AbstractInterface* iface; QHashIterator iterI(consumptionPattern); while (iterI.hasNext()) { iterI.next(); iface = reference->getIfaceFromName(iterI.key()); - if (iface == NULL) return false; + if (iface == NULL) { + cout << "cannot found an input ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } } QHashIterator iterO(productionPattern); while (iterO.hasNext()) { iterO.next(); iface = reference->getIfaceFromName(iterO.key()); - if (iface == NULL) return false; + if (iface == NULL) { + cout << "cannot found an output ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } } return true; } -void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &path) throw(Exception) { - - block = _block; - - QFile implFile(xmlFile); - - // reading in into QDomDocument - QDomDocument document("implFile"); - - if (!implFile.open(QIODevice::ReadOnly)) { - throw(Exception(IMPLFILE_NOACCESS)); - } - if (!document.setContent(&implFile)) { - implFile.close(); - throw(Exception(IMPLFILE_NOACCESS)); - } - implFile.close(); - - bool genController = false; - QString coreFile = ""; - QString controllerFile = ""; - - if (reference->isWBConfigurable()) { - genController = true; - controllerFile = path; - controllerFile.append(block->getName()); - controllerFile.append("_ctrl.vhd"); - } - else { - controllerFile = "nofile.vhd"; - } - coreFile = path; - coreFile.append(block->getName()); - coreFile.append(".vhd"); - - QFile vhdlCore(coreFile); - QFile vhdlController(controllerFile); - - if (!vhdlCore.open(QIODevice::WriteOnly)) { - throw(Exception(VHDLFILE_NOACCESS)); - } - - if (genController) { - if (!vhdlController.open(QIODevice::WriteOnly)) { - throw(Exception(VHDLFILE_NOACCESS)); - } - } - QTextStream outCore(&vhdlCore); - QTextStream outController; - if (genController) { - outController.setDevice(&vhdlController); - } - - try { - - - //Get the root element - QDomElement impl = document.documentElement(); - QDomElement eltComments = impl.firstChildElement("comments"); - generateComments(eltComments, coreFile, outCore); - QDomElement eltLibs = eltComments.nextSiblingElement("libraries"); - generateLibraries(eltLibs, outCore); - generateEntity(outCore, genController); - QDomElement eltArch = eltLibs.nextSiblingElement("architecture"); - generateArchitecture(eltArch, outCore); - if (genController) { - generateController(outController); - } - } - catch(Exception err) { - throw(err); - } - - vhdlCore.close(); - vhdlController.close(); -} - -// This function generates the comments part of the VHDL document -void BlockImplementation::generateComments(QDomElement &elt, QString coreFile, QTextStream& out) throw(Exception) { - - for(int i = 0; i < 50; i++) { - out << "--"; - } - out << "\n--\n"; - QString fileName = coreFile; - out << "-- File : " << fileName << "\n"; - out << "--\n"; - QDomElement eltAuthor = elt.firstChildElement("author"); - QString firstName = eltAuthor.attribute("firstname",""); - QString lastName = eltAuthor.attribute("lastname",""); - QString mail = eltAuthor.attribute("mail",""); - out << "-- Author(s) : "<getName(); - //QList listParams = reference->getParameters(); - QList listInputs = reference->getInputs(); - QList listOutputs = reference->getOutputs(); - QList listBidirs = reference->getBidirs(); - QString typePort, namePort; - - out << "entity " << nameEnt << " is\n"; - - - /* TODO : rewrite the generation to take into acocunt the new object hierarchy */ - - // Generation of the generics - QList listGenerics = reference->getGenericParameters(); - if ((!listGenerics.isEmpty()) || (hasController)) { - out << " generic (" << endl; - if (hasController) { - out << " wb_data_width : integer = 16;" << endl; - out << " wb_addr_width : integer = 12"; - if (!listGenerics.isEmpty()) out << ";"; - out << endl; - } - for(i=0;itoVHDL(BlockParameter::Entity, 0); - } - out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); - - out << " );" << endl; - } - - out << " port (" << endl; - - // Generation of the clk & rst signals - out << " -- clk/rst" << endl; - for(int i = 0; i < listInputs.size(); i++) { - if(listInputs.at(i)->getPurpose() == AbstractInterface::Clock || listInputs.at(i)->getPurpose() == AbstractInterface::Reset) { - out << " " << listInputs.at(i)->getName() << " : in std_logic;" << endl; - } - } - - if (hasController) { - // Generation of the wishbone signals - out << " -- registers r/w via wishbone" << endl; - QList listWB = reference->getWishboneParameters(); - for(i=0;itoVHDL(BlockParameter::Entity, 0); - } - out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); - } - - - // Generation of the data signals - out << "-- data ports\n"; - for(int i = 0; i < listInputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName())); - if(listInputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listInputs.at(i)->getWidth()); - if(listInputs.at(i)->getPurpose() == 1) - out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n"; - } - - for(int i = 0; i < listOutputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName())); - if(listOutputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listOutputs.at(i)->getWidth()); - if(listOutputs.at(i)->getPurpose() == 1) - out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n"; - } - - for(int i = 0; i < listBidirs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName())); - if(listBidirs.at(i)->getWidth().compare(("1"))) - typePort = "std_logic"; - else - typePort = calculateWidth((listBidirs.at(i)->getWidth())); - if(listBidirs.at(i)->getPurpose() == 1) - out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n"; - } -} - -// This function generates the architecture part of the VHDL document -void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) { - - QString expr; - QDomElement eltArch = elt.nextSiblingElement("architecture"); - out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n"; - QString implText = eltArch.text(); - QStringList listLine = implText.split("\n"); - for(int i =0; i < listLine.size(); i++) { - if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) { - while(listLine.at(i).compare("@endforeach") != -1) { - expr = expr + listLine.at(i) + '\n'; - i++; - } - expr = expr + listLine.at(i); - out << evalComplex(expr, 1) << '\n'; - } - if(listLine.at(i).contains(QRegularExpression("@caseeach{")) != -1) { - while(listLine.at(i).compare("@endcaseeach") != -1) { - expr = expr + listLine.at(i) + '\n'; - i++; - } - expr = expr + listLine.at(i); - out << evalComplex(expr, 2) << '\n'; - } - - if(listLine.at(i).contains('@') == -1) - out << listLine.at(i) << "\n"; - else - out << eval(listLine.at(i), out) << "\n"; - } -} - -void BlockImplementation::generateController(QTextStream &out) throw(Exception) { -} - QString BlockImplementation::eval(QString line, QTextStream& out) { QString res, s, begLine, endLine, expr; evaluator->setExpression(line); @@ -568,6 +332,7 @@ QDataStream& operator<<(QDataStream &out, const BlockImplementation &impl) { toWrite << impl.referenceXml; toWrite << impl.referenceMd5; // saving patterns + toWrite << impl.noPatterns; toWrite << impl.delta; toWrite << impl.consumptionPattern; toWrite << impl.productionPattern; @@ -590,6 +355,7 @@ QDataStream& operator>>(QDataStream &in, BlockImplementation &impl) { in >> impl.referenceXml; in >> impl.referenceMd5; // loading patterns + in >> impl.noPatterns; in >> impl.delta; in >> impl.consumptionPattern; in >> impl.productionPattern;