X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/5d4e709cb8d460b2efc083e6e7999f1c3a0eb602..e9f53048b4a0192d95382277e8f40e850998b256:/BlockImplementation.cpp?ds=sidebyside diff --git a/BlockImplementation.cpp b/BlockImplementation.cpp index e6b61ca..1553ebb 100644 --- a/BlockImplementation.cpp +++ b/BlockImplementation.cpp @@ -52,8 +52,9 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { } QDomElement eltProd = eltCons.nextSiblingElement("production"); + productionCounter = eltProd.attribute("counter","none"); - QDomNodeList listNodeOutput = eltCons.elementsByTagName("output"); + QDomNodeList listNodeOutput = eltProd.elementsByTagName("output"); for(int i=0; i<listNodeOutput.size(); i++) { QDomNode node = listNodeOutput.at(i); QDomElement elt = node.toElement(); @@ -62,24 +63,41 @@ void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { QString patternStr = elt.attribute("pattern","none"); productionPattern.insert(nameStr,patternStr); } + cout << "patterns summary:" << endl; + QHashIterator<QString,QString> iterP(productionPattern); + while (iterP.hasNext()) { + iterP.next(); + cout << qPrintable(iterP.key()) << " -> " << qPrintable(iterP.value()) << endl; + } cout << "impls patterns read correctly" << endl; } bool BlockImplementation::checkPatterns() { - if (reference == NULL) return false; + + + if (reference == NULL) { + cout << "no ref. while checking patterns of implementation " << endl; + return false; + } AbstractInterface* iface; QHashIterator<QString,QString> iterI(consumptionPattern); while (iterI.hasNext()) { iterI.next(); iface = reference->getIfaceFromName(iterI.key()); - if (iface == NULL) return false; + if (iface == NULL) { + cout << "cannot found an input ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } } QHashIterator<QString,QString> iterO(productionPattern); while (iterO.hasNext()) { iterO.next(); iface = reference->getIfaceFromName(iterO.key()); - if (iface == NULL) return false; + if (iface == NULL) { + cout << "cannot found an output ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } } return true; } @@ -109,6 +127,7 @@ void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &p if (reference->isWBConfigurable()) { genController = true; controllerFile = path; + controllerFile += "/"; controllerFile.append(block->getName()); controllerFile.append("_ctrl.vhd"); } @@ -116,6 +135,7 @@ void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &p controllerFile = "nofile.vhd"; } coreFile = path; + coreFile += "/"; coreFile.append(block->getName()); coreFile.append(".vhd"); @@ -162,63 +182,63 @@ void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &p } // This function generates the comments part of the VHDL document -void BlockImplementation::generateComments(QDomElement &elt, QString coreFile, QTextStream& out) throw(Exception) { +void BlockImplementation::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) { for(int i = 0; i < 50; i++) { out << "--"; } - out << "\n--\n"; + out << "\n--" << endl; QString fileName = coreFile; - out << "-- File : " << fileName << "\n"; - out << "--\n"; + out << "-- File : " << fileName << endl; + out << "--" << endl; QDomElement eltAuthor = elt.firstChildElement("author"); QString firstName = eltAuthor.attribute("firstname",""); QString lastName = eltAuthor.attribute("lastname",""); QString mail = eltAuthor.attribute("mail",""); - out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")\n"; - out << "--\n"; + out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")" << endl; + out << "--" << endl; QDomElement eltDate = eltAuthor.nextSiblingElement("date"); QString crea = eltDate.attribute("creation",""); - out << "-- Creation Date : "<<crea<<"\n"; - out << "--\n"; + out << "-- Creation Date : "<<crea<< endl; + out << "--" << endl; QDomElement eltRelated = eltDate.nextSiblingElement("related_files"); QString relateds = eltRelated.attribute("list",""); - out << "-- Related files :\n"<<relateds<<"\n"; - out << "--\n"; + out << "-- Related files :\n"<<relateds<<endl; + out << "--" << endl; QDomElement eltDesc = eltRelated.nextSiblingElement("description"); QDomElement desc = eltDesc.firstChildElement(); QString descTxt = desc.text(); - out << "-- Decription :\n"<<descTxt<<"\n"; - out << "--\n"; + out << "-- Decription :\n"<<descTxt<<endl; + out << "--" << endl; QDomElement eltNote = eltDesc.nextSiblingElement("description"); QDomElement note = eltNote.firstChildElement(); QString noteTxt = note.text(); - out << "-- Note :\n"<<noteTxt<<"\n"; - out << "--\n"; + out << "-- Note :\n"<<noteTxt<<endl; + out << "--" << endl; for(int i = 0; i < 50; i++) { out << "--"; } - out << "\n\n"; + out << endl << endl; } // This function generates the library part of the VHDL document -void BlockImplementation::generateLibraries(QDomElement &elt, QTextStream& out) throw(Exception) { +void BlockImplementation::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) { QDomNodeList listLib = elt.elementsByTagName("library"); for(int i = 0; i < listLib.length(); i++) { QDomNode nodeLib = listLib.item(i); QDomElement eltLib = nodeLib.toElement(); - QString nameLib = eltLib.attribute("name", ""); - out << "library " << nameLib << ";\n"; + QString nameLib = eltLib.attribute("name","none"); + out << "library " << nameLib << ";" << endl; QDomNodeList listPack = eltLib.elementsByTagName("package"); for(int j = 0; j < listPack.length(); j++) { QDomNode nodePack = listPack.item(j); QDomElement eltPack = nodePack.toElement(); - QString namePack = eltPack.attribute("name", ""); - QString usePack = elt.attribute("use",""); - out << "use " << nameLib << "." << namePack << "." << usePack << ";\n"; + QString namePack = eltPack.attribute("name","none"); + QString usePack = eltPack.attribute("use","none"); + out << "use " << nameLib << "." << namePack << "." << usePack << endl; } - out << "\n"; + out << endl; } } @@ -226,20 +246,20 @@ void BlockImplementation::generateLibraries(QDomElement &elt, QTextStream& out) void BlockImplementation::generateEntity(QTextStream& out, bool hasController) throw(Exception) { int i=0; - nameEnt = reference->getName(); + nameEnt = block->getName(); //QList<BlockParameter*> listParams = reference->getParameters(); - QList<AbstractInterface*> listInputs = reference->getInputs(); - QList<AbstractInterface*> listOutputs = reference->getOutputs(); - QList<AbstractInterface*> listBidirs = reference->getBidirs(); + QList<AbstractInterface*> listInputs = block->getInputs(); + QList<AbstractInterface*> listOutputs = block->getOutputs(); + QList<AbstractInterface*> listBidirs = block->getBidirs(); QString typePort, namePort; - out << "entity " << nameEnt << " is\n"; + out << "entity " << nameEnt << " is" << endl; /* TODO : rewrite the generation to take into acocunt the new object hierarchy */ // Generation of the generics - QList<BlockParameter*> listGenerics = reference->getGenericParameters(); + QList<BlockParameter*> listGenerics = block->getGenericParameters(); if ((!listGenerics.isEmpty()) || (hasController)) { out << " generic (" << endl; if (hasController) { @@ -249,9 +269,9 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t out << endl; } for(i=0;i<listGenerics.size()-1;i++) { - out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0); + out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl; } - out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); + out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; out << " );" << endl; } @@ -260,9 +280,9 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t // Generation of the clk & rst signals out << " -- clk/rst" << endl; - for(int i = 0; i < listInputs.size(); i++) { - if(listInputs.at(i)->getPurpose() == AbstractInterface::Clock || listInputs.at(i)->getPurpose() == AbstractInterface::Reset) { - out << " " << listInputs.at(i)->getName() << " : in std_logic;" << endl; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) { + out << " " << iface->getName() << " : in std_logic;" << endl; } } @@ -271,55 +291,98 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t out << " -- registers r/w via wishbone" << endl; QList<BlockParameter*> listWB = reference->getWishboneParameters(); for(i=0;i<listWB.size()-1;i++) { - out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0); + out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl; } - out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); + out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; } - // Generation of the data signals - out << "-- data ports\n"; - for(int i = 0; i < listInputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName())); - if(listInputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listInputs.at(i)->getWidth()); - if(listInputs.at(i)->getPurpose() == 1) - out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n"; + int count = 0; + foreach(AbstractInterface* iface, block->getInterfaces()) { + if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++; } + // Generation of the data/control signals - for(int i = 0; i < listOutputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName())); - if(listOutputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listOutputs.at(i)->getWidth()); - if(listOutputs.at(i)->getPurpose() == 1) - out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n"; - } + int flag = 0; + bool first = true; - for(int i = 0; i < listBidirs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName())); - if(listBidirs.at(i)->getWidth().compare(("1"))) - typePort = "std_logic"; - else - typePort = calculateWidth((listBidirs.at(i)->getWidth())); - if(listBidirs.at(i)->getPurpose() == 1) - out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n"; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- input data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << " -- input control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- output data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << " -- output control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listBidirs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- bidirs data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + out << " );" << endl << endl; + out << "end " << nameEnt << ";" << endl << endl; } // This function generates the architecture part of the VHDL document -void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) { +void BlockImplementation::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) { QString expr; - QDomElement eltArch = elt.nextSiblingElement("architecture"); - out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n"; - QString implText = eltArch.text(); - QStringList listLine = implText.split("\n"); + QString code = elt.text(); + cout << qPrintable(code) << endl; + out << "architecture rtl of " << nameEnt << " is" << endl; + + QStringList listLine = code.split("\n"); for(int i =0; i < listLine.size(); i++) { - if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) { + QString line = listLine.at(i).simplified(); + + /* + if(listLine.at(i).contains(QRegularExpression("@foreach{"))) { while(listLine.at(i).compare("@endforeach") != -1) { expr = expr + listLine.at(i) + '\n'; i++; @@ -327,7 +390,7 @@ void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& ou expr = expr + listLine.at(i); out << evalComplex(expr, 1) << '\n'; } - if(listLine.at(i).contains(QRegularExpression("@caseeach{")) != -1) { + if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) { while(listLine.at(i).compare("@endcaseeach") != -1) { expr = expr + listLine.at(i) + '\n'; i++; @@ -335,11 +398,10 @@ void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& ou expr = expr + listLine.at(i); out << evalComplex(expr, 2) << '\n'; } - - if(listLine.at(i).contains('@') == -1) - out << listLine.at(i) << "\n"; - else - out << eval(listLine.at(i), out) << "\n"; +*/ + if(line.contains("@{")) { + out << line << endl; + } } }