X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/60c13e8b4c7ea3d595969c1e7c0a28b068a17ca6..4327c2b8817b627249d98d889835726217c81a4e:/AbstractBlock.h?ds=sidebyside diff --git a/AbstractBlock.h b/AbstractBlock.h index 8f09410..efbd474 100644 --- a/AbstractBlock.h +++ b/AbstractBlock.h @@ -9,6 +9,7 @@ #include "AbstractInterface.h" class AbstractInterface; class BlockParameter; +class Graph; #define AB_TO_REF(ptr) ((ReferenceBlock*)ptr) #define AB_TO_FUN(ptr) ((FunctionalBlock*)ptr) @@ -26,7 +27,7 @@ public: enum SpecialType { NotSpecial = 0, Source = 1, Sink = 2, ClkConvert = 3 }; - AbstractBlock(); + AbstractBlock(Graph* _graph); //AbstractBlock(const QString& _name); virtual ~AbstractBlock(); @@ -35,6 +36,7 @@ public: inline int getSpecialType() { return specialType; } inline QString getVersion() { return version; } inline int nbParameters() { return params.size(); } + inline Graph* getGraph() { return graph; } inline QList getInputs() { return inputs; } inline QList getOutputs() { return outputs; } @@ -84,9 +86,7 @@ public: * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces * \param idBlockClk is the id of the clock interface (there may be severals) * \param idGen is the id of the clkrstgen block - */ - void connectClock(QString clkName, int idGen = 0) throw(Exception); - void connectReset(QString rstName, int idGen = 0) throw(Exception); + */ virtual QList getExternalResources() = 0; // returns the list of all external files needed for VHDL generation virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference @@ -112,6 +112,7 @@ protected: QString name; int specialType; QString version; + Graph* graph; // parameters QList params;