X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/6e2b3026c6a496e81642c373796bd39dad33d2a6..2bdaa0aa3fab52f0808f60d9bbdabcd56d0efae9:/AbstractBlock.h?ds=sidebyside

diff --git a/AbstractBlock.h b/AbstractBlock.h
index 5f2acb5..fe3f90e 100644
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -59,8 +59,15 @@ public:
   bool isWBConfigurable();
 
   // others
-  void connectClkReset() throw(Exception);  
 
+  /*!
+   * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces
+   * \param idBlockClk is the id of the clock interface (there may be severals)
+   * \param idGen is the id of the clkrstgen block
+  */
+  void connectClock(QString clkName, int idGen = 0) throw(Exception);
+  void connectReset(QString rstName, int idGen = 0) throw(Exception);
+  virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation
   virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code
   void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference
   void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference