X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/756baf5c8eaf003e8271dab9c395de2b0e704857..2bdaa0aa3fab52f0808f60d9bbdabcd56d0efae9:/AbstractBlock.h?ds=sidebyside

diff --git a/AbstractBlock.h b/AbstractBlock.h
index 042a598..fe3f90e 100644
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -4,6 +4,7 @@
 #include <iostream>
 
 #include <QtCore>
+#include <QtXml>
 
 #include "AbstractInterface.h"
 class AbstractInterface;
@@ -20,8 +21,10 @@ class AbstractBlock {
 
 public:  
       
+  enum BlockVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Architecture = 3 }; // NB : 3 is when creating an instance of the block that owns this iface
+
   AbstractBlock();
-  AbstractBlock(const QString& _name);
+  //AbstractBlock(const QString& _name);
   virtual ~AbstractBlock();
 
   // getters
@@ -30,7 +33,7 @@ public:
   inline QList<BlockParameter *> getParameters() { return params; }
   inline QList<AbstractInterface*> getInputs() { return inputs; }
   inline QList<AbstractInterface*> getOutputs() { return outputs; }
-  inline QList<AbstractInterface*> getBidirs() { return bidirs; }
+  inline QList<AbstractInterface*> getBidirs() { return bidirs; }  
   QList<BlockParameter *> getUserParameters();
   QList<BlockParameter *> getGenericParameters();
   QList<BlockParameter *> getPortParameters();
@@ -56,7 +59,18 @@ public:
   bool isWBConfigurable();
 
   // others
-  static QString normalizeName(const QString& name);
+
+  /*!
+   * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces
+   * \param idBlockClk is the id of the clock interface (there may be severals)
+   * \param idGen is the id of the clkrstgen block
+  */
+  void connectClock(QString clkName, int idGen = 0) throw(Exception);
+  void connectReset(QString rstName, int idGen = 0) throw(Exception);
+  virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation
+  virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code
+  void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference
+  void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference
 
   virtual void parametersValidation(QList<AbstractBlock*>* checkedBlocks, QList<AbstractBlock*>* blocksToConfigure) = 0; // ugly but usefull   
 
@@ -101,6 +115,11 @@ protected:
   // NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents
   AbstractBlock* parent;
 
+  virtual void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) = 0; // generates comments from <comments> element
+  virtual void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) = 0; // generates libraries from <libraries> element  
+  virtual void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) = 0; // generate the architecture using <architecture> element
+  virtual void generateController(QTextStream& out) throw(Exception) = 0; // generate the wishbone controller of the block
+  virtual void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception) = 0; // generate the entity/compo body using reference
 
 };