X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/7b1c7e44123b9b2626205a89e27b2a4712ea30c6..e40a5399ec7887c2606f18575c809b0d05b09278:/AbstractBlock.h diff --git a/AbstractBlock.h b/AbstractBlock.h index 2bb2717..fe3f90e 100644 --- a/AbstractBlock.h +++ b/AbstractBlock.h @@ -4,6 +4,7 @@ #include #include +#include #include "AbstractInterface.h" class AbstractInterface; @@ -20,8 +21,10 @@ class AbstractBlock { public: + enum BlockVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Architecture = 3 }; // NB : 3 is when creating an instance of the block that owns this iface + AbstractBlock(); - AbstractBlock(const QString& _name); + //AbstractBlock(const QString& _name); virtual ~AbstractBlock(); // getters @@ -30,18 +33,21 @@ public: inline QList getParameters() { return params; } inline QList getInputs() { return inputs; } inline QList getOutputs() { return outputs; } - inline QList getBidirs() { return bidirs; } + inline QList getBidirs() { return bidirs; } QList getUserParameters(); QList getGenericParameters(); QList getPortParameters(); QList getWishboneParameters(); inline AbstractBlock* getParent() { return parent; } inline bool getPatternComputed() { return patternComputed; } + inline int getTraversalLevel() { return traversalLevel; } // setters void setName(const QString& str); virtual void setParent(AbstractBlock* _parent); inline void setPatternComputed(bool state) { patternComputed = state; } + inline void resetTraversalLevel() { traversalLevel = -1; } + inline void setTraversalLevel(int level) { traversalLevel = level; } // testers virtual bool isReferenceBlock(); @@ -53,6 +59,19 @@ public: bool isWBConfigurable(); // others + + /*! + * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces + * \param idBlockClk is the id of the clock interface (there may be severals) + * \param idGen is the id of the clkrstgen block + */ + void connectClock(QString clkName, int idGen = 0) throw(Exception); + void connectReset(QString rstName, int idGen = 0) throw(Exception); + virtual QList getExternalResources() = 0; // returns the list of all external files needed for VHDL generation + virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code + void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference + void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference + virtual void parametersValidation(QList* checkedBlocks, QList* blocksToConfigure) = 0; // ugly but usefull void addParameter(BlockParameter *param); @@ -72,6 +91,7 @@ public: // patterns virtual void checkInputPatternCompatibility() throw(Exception) = 0; virtual void computeOutputPattern(int nbExec = -1) throw(Exception) = 0; + virtual void computeAdmittanceDelays() throw(Exception) = 0; protected: @@ -90,9 +110,17 @@ protected: // patterns bool patternComputed; + int traversalLevel; // the level (0, 1, ...) during the traversal of the graph // NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents AbstractBlock* parent; + + virtual void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) = 0; // generates comments from element + virtual void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) = 0; // generates libraries from element + virtual void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) = 0; // generate the architecture using element + virtual void generateController(QTextStream& out) throw(Exception) = 0; // generate the wishbone controller of the block + virtual void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception) = 0; // generate the entity/compo body using reference + }; #endif // __ABSTRACTBLOCK_H__