X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/8d3e09e430e829b9d847847334cbfe37790baca3..4cf57e6db08da791233d75237f62e74bc88dd427:/BlockImplementation.cpp?ds=sidebyside diff --git a/BlockImplementation.cpp b/BlockImplementation.cpp index af06ef3..f71297f 100644 --- a/BlockImplementation.cpp +++ b/BlockImplementation.cpp @@ -5,10 +5,13 @@ #include "ReferenceInterface.h" #include "FunctionalInterface.h" #include "BlockParameter.h" +#include BlockImplementation::BlockImplementation(const QString& _xmlFile) { - xmlFile = _xmlFile; + xmlFile = _xmlFile; + productionCounter = ""; + delta = ""; evaluator = new ArithmeticEvaluator; evaluator->setVariableMarkers("@$"); @@ -16,32 +19,87 @@ BlockImplementation::BlockImplementation(const QString& _xmlFile) { BlockImplementation::BlockImplementation(const QString& _xmlFile, const QString &_referenceXml, const QString &_referenceMd5) { xmlFile = _xmlFile; + productionCounter = ""; + delta = ""; referenceXml = _referenceXml; referenceMd5 = _referenceMd5; } -void BlockImplementation::assignPatterns(FunctionalBlock *_block) throw(Exception) { +void BlockImplementation::loadPatterns(QDomElement& root) throw(Exception) { + + QDomNodeList patternNode = root.elementsByTagName("patterns"); - block = _block; + if (patternNode.isEmpty()) { + cout << "impl has no patterns" << endl; + return; + } + + QDomElement patternElt = patternNode.at(0).toElement(); + + QDomElement eltDelta = patternElt.firstChildElement("delta"); + delta = eltDelta.attribute("value","none"); + + QDomElement eltCons = eltDelta.nextSiblingElement("consumption"); + + QDomNodeList listNodeInput = eltCons.elementsByTagName("input"); + for(int i=0; i iterP(productionPattern); + while (iterP.hasNext()) { + iterP.next(); + cout << qPrintable(iterP.key()) << " -> " << qPrintable(iterP.value()) << endl; + } + cout << "impls patterns read correctly" << endl; +} - QFile implFile(xmlFile); +bool BlockImplementation::checkPatterns() { - // reading in into QDomDocument - QDomDocument document("implFile"); - if (!implFile.open(QIODevice::ReadOnly)) { - throw(Exception(IMPLFILE_NOACCESS)); + if (reference == NULL) { + cout << "no ref. while checking patterns of implementation " << endl; + return false; } - if (!document.setContent(&implFile)) { - implFile.close(); - throw(Exception(IMPLFILE_NOACCESS)); - } - implFile.close(); - QDomElement impl = document.documentElement(); - QDomNodeList patternNode = impl.elementsByTagName("patterns"); - if (patternNode.isEmpty()) return; - QDomElement patternElt = patternNode.at(0).toElement(); + AbstractInterface* iface; + QHashIterator iterI(consumptionPattern); + while (iterI.hasNext()) { + iterI.next(); + iface = reference->getIfaceFromName(iterI.key()); + if (iface == NULL) { + cout << "cannot found an input ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } + } + QHashIterator iterO(productionPattern); + while (iterO.hasNext()) { + iterO.next(); + iface = reference->getIfaceFromName(iterO.key()); + if (iface == NULL) { + cout << "cannot found an output ref. iface for impl. iface " << qPrintable(iterI.key()) << endl; + return false; + } + } + return true; } void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &path) throw(Exception) { @@ -168,17 +226,17 @@ void BlockImplementation::generateLibraries(QDomElement &elt, QTextStream& out) for(int i = 0; i < listLib.length(); i++) { QDomNode nodeLib = listLib.item(i); QDomElement eltLib = nodeLib.toElement(); - QString nameLib = eltLib.attribute("name", ""); + QString nameLib = eltLib.attribute("name","none"); out << "library " << nameLib << ";\n"; QDomNodeList listPack = eltLib.elementsByTagName("package"); for(int j = 0; j < listPack.length(); j++) { QDomNode nodePack = listPack.item(j); QDomElement eltPack = nodePack.toElement(); - QString namePack = eltPack.attribute("name", ""); - QString usePack = elt.attribute("use",""); - out << "use " << nameLib << "." << namePack << "." << usePack << ";\n"; + QString namePack = eltPack.attribute("name","none"); + QString usePack = eltPack.attribute("use","none"); + out << "use " << nameLib << "." << namePack << "." << usePack << endl; } - out << "\n"; + out << endl; } } @@ -186,11 +244,11 @@ void BlockImplementation::generateLibraries(QDomElement &elt, QTextStream& out) void BlockImplementation::generateEntity(QTextStream& out, bool hasController) throw(Exception) { int i=0; - nameEnt = reference->getName(); + nameEnt = block->getName(); //QList listParams = reference->getParameters(); - QList listInputs = reference->getInputs(); - QList listOutputs = reference->getOutputs(); - QList listBidirs = reference->getBidirs(); + QList listInputs = block->getInputs(); + QList listOutputs = block->getOutputs(); + QList listBidirs = block->getBidirs(); QString typePort, namePort; out << "entity " << nameEnt << " is\n"; @@ -199,7 +257,7 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t /* TODO : rewrite the generation to take into acocunt the new object hierarchy */ // Generation of the generics - QList listGenerics = reference->getGenericParameters(); + QList listGenerics = block->getGenericParameters(); if ((!listGenerics.isEmpty()) || (hasController)) { out << " generic (" << endl; if (hasController) { @@ -209,9 +267,9 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t out << endl; } for(i=0;itoVHDL(BlockParameter::Entity, 0); + out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl; } - out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); + out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; out << " );" << endl; } @@ -220,9 +278,9 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t // Generation of the clk & rst signals out << " -- clk/rst" << endl; - for(int i = 0; i < listInputs.size(); i++) { - if(listInputs.at(i)->getPurpose() == AbstractInterface::Clock || listInputs.at(i)->getPurpose() == AbstractInterface::Reset) { - out << " " << listInputs.at(i)->getName() << " : in std_logic;" << endl; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) { + out << " " << iface->getName() << " : in std_logic;" << endl; } } @@ -231,55 +289,98 @@ void BlockImplementation::generateEntity(QTextStream& out, bool hasController) t out << " -- registers r/w via wishbone" << endl; QList listWB = reference->getWishboneParameters(); for(i=0;itoVHDL(BlockParameter::Entity, 0); + out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl; } - out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma); + out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl; } - // Generation of the data signals - out << "-- data ports\n"; - for(int i = 0; i < listInputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName())); - if(listInputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listInputs.at(i)->getWidth()); - if(listInputs.at(i)->getPurpose() == 1) - out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n"; + int count = 0; + foreach(AbstractInterface* iface, block->getInterfaces()) { + if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++; } + // Generation of the data/control signals - for(int i = 0; i < listOutputs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName())); - if(listOutputs.at(i)->getWidth().compare("1")) - typePort = "std_logic"; - else - typePort = calculateWidth(listOutputs.at(i)->getWidth()); - if(listOutputs.at(i)->getPurpose() == 1) - out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n"; - } + int flag = 0; + bool first = true; - for(int i = 0; i < listBidirs.size(); i++) { - namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName())); - if(listBidirs.at(i)->getWidth().compare(("1"))) - typePort = "std_logic"; - else - typePort = calculateWidth((listBidirs.at(i)->getWidth())); - if(listBidirs.at(i)->getPurpose() == 1) - out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n"; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- input data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listInputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << " -- input control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- output data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } } + first = true; + foreach(AbstractInterface* iface, listOutputs) { + if(iface->getPurpose() == AbstractInterface::Control) { + if (first) { + out << " -- output control ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + first = true; + foreach(AbstractInterface* iface, listBidirs) { + if(iface->getPurpose() == AbstractInterface::Data) { + if (first) { + out << " -- bidirs data ports" << endl; + first = false; + } + count--; + if (count == 0) flag = AbstractInterface::NoComma; + out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl; + } + } + out << " );" << endl << endl; + out << "end " << nameEnt << ";" << endl << endl; } // This function generates the architecture part of the VHDL document void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) { QString expr; - QDomElement eltArch = elt.nextSiblingElement("architecture"); - out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n"; - QString implText = eltArch.text(); - QStringList listLine = implText.split("\n"); + QString code = elt.text(); + cout << qPrintable(code) << endl; + out << "architecture rtl of " << nameEnt << " is" << endl; + + QStringList listLine = code.split("\n"); for(int i =0; i < listLine.size(); i++) { - if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) { + QString line = listLine.at(i).simplified(); + + /* + if(listLine.at(i).contains(QRegularExpression("@foreach{"))) { while(listLine.at(i).compare("@endforeach") != -1) { expr = expr + listLine.at(i) + '\n'; i++; @@ -287,7 +388,7 @@ void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& ou expr = expr + listLine.at(i); out << evalComplex(expr, 1) << '\n'; } - if(listLine.at(i).contains(QRegularExpression("@caseeach{")) != -1) { + if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) { while(listLine.at(i).compare("@endcaseeach") != -1) { expr = expr + listLine.at(i) + '\n'; i++; @@ -295,11 +396,10 @@ void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& ou expr = expr + listLine.at(i); out << evalComplex(expr, 2) << '\n'; } - - if(listLine.at(i).contains('@') == -1) - out << listLine.at(i) << "\n"; - else - out << eval(listLine.at(i), out) << "\n"; +*/ + if(line.contains("@{")) { + out << line << endl; + } } } @@ -527,7 +627,12 @@ QDataStream& operator<<(QDataStream &out, const BlockImplementation &impl) { toWrite << impl.xmlFile; toWrite << impl.referenceXml; toWrite << impl.referenceMd5; - + // saving patterns + toWrite << impl.delta; + toWrite << impl.consumptionPattern; + toWrite << impl.productionPattern; + toWrite << impl.productionCounter; + out << blockData; return out; @@ -544,6 +649,11 @@ QDataStream& operator>>(QDataStream &in, BlockImplementation &impl) { in >> impl.xmlFile; in >> impl.referenceXml; in >> impl.referenceMd5; + // loading patterns + in >> impl.delta; + in >> impl.consumptionPattern; + in >> impl.productionPattern; + in >> impl.productionCounter; return in; }