X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/8f0bedf735fe2b306c11c3f4a168245a05e37ccd..14cd6d834ab531525a51c6a6992583b3e9143e02:/DelayInputModifier.cpp?ds=inline diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp index a90695a..a60d7e2 100644 --- a/DelayInputModifier.cpp +++ b/DelayInputModifier.cpp @@ -34,23 +34,30 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) { dm1.setNum(delayLength-1); dm2.setNum(delayLength-2); QString ret=""; + QString clkName = "clk"; + QString resetName = "reset"; + if (toIface->getOwner()->getParent()->isTopGroupBlock()) { + clkName = "from_clkrstgen_clk"; + resetName ="from_clkrstgen_reset"; + } + if (context == Architecture) { - ret = toName + "_mod_process : process(clk,reset)\n"; + ret = toName + "_mod_process : process("+clkName+","+resetName+")\n"; ret += " begin\n"; - ret += " if reset = '1' then\n"; + ret += " if "+resetName+" = '1' then\n"; ret += " "+toName+"_dly <= (others => (others => '0'));\n"; ret += " "+toCtlName+"_dly <= (others => '0');\n"; ret += " "+toName+"_mod <= (others => '0');\n"; ret += " "+toCtlName+"_mod <= '0';\n"; - ret += " elsif rising_edge(clk) then\n"; + ret += " elsif rising_edge("+clkName+") then\n"; ret += " "+toName+"_mod <= "+toName+"_dly("+dm1+");\n"; ret += " "+toCtlName+"_mod <= "+toCtlName+"_dly("+dm1+");\n"; ret += " "+toName+"_dly(0) <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n"; ret += " "+toCtlName+"_dly(0) <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n"; ret += " "+toName+"_dly(1 to "+dm1+") <= "+toName+"_dly(0 to "+dm2+");\n"; ret += " "+toCtlName+"_dly(1 to "+dm1+") <= "+toCtlName+"_dly(0 to "+dm2+");\n"; - ret += " end if\n"; - ret += " end process "+toName + "_mod_process\n"; + ret += " end if;\n"; + ret += " end process "+toName + "_mod_process;\n"; } else if (context == Signal) { QString sig = toIface->toVHDL(AbstractInterface::Signal,0);