X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/8f0bedf735fe2b306c11c3f4a168245a05e37ccd..2bdaa0aa3fab52f0808f60d9bbdabcd56d0efae9:/DelayInputModifier.cpp?ds=sidebyside

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index a90695a..db89107 100644
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -29,28 +29,35 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
   ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());
   QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();
   QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();
-  QString dm1 = "";
   QString dm2 = "";
-  dm1.setNum(delayLength-1);
+  QString dm3 = "";
   dm2.setNum(delayLength-2);
+  dm3.setNum(delayLength-3);
   QString ret="";
+  QString clkName = "clk";
+  QString resetName = "reset";
+  if (toIface->getOwner()->getParent()->isTopGroupBlock()) {
+    clkName = "from_clkrstgen_clk";
+    resetName ="from_clkrstgen_reset";
+  }
+
   if (context == Architecture) {
-    ret = toName + "_mod_process : process(clk,reset)\n";
+    ret = toName + "_mod_process : process("+clkName+","+resetName+")\n";
     ret += "  begin\n";
-    ret += "    if reset = '1' then\n";
+    ret += "    if "+resetName+" = '1' then\n";
     ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";
     ret += "      "+toCtlName+"_dly  <= (others => '0');\n";
     ret += "      "+toName+"_mod     <= (others => '0');\n";
     ret += "      "+toCtlName+"_mod  <= '0';\n";
-    ret += "    elsif rising_edge(clk) then\n";
-    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";
-    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";
+    ret += "    elsif rising_edge("+clkName+") then\n";
+    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm2+");\n";
+    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm2+");\n";
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";
-    ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";
-    ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";
-    ret += "    end if\n";
-    ret += "  end process "+toName + "_mod_process\n";
+    ret += "      "+toName+"_dly(1 to "+dm2+")  <= "+toName+"_dly(0 to "+dm3+");\n";
+    ret += "      "+toCtlName+"_dly(1 to "+dm2+")  <= "+toCtlName+"_dly(0 to "+dm3+");\n";
+    ret += "    end if;\n";
+    ret += "  end process "+toName + "_mod_process;\n";
   }
   else if (context == Signal) {
     QString sig = toIface->toVHDL(AbstractInterface::Signal,0);
@@ -61,8 +68,8 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "  signal "+sig+"\n";
     QString wStr="";
     wStr.setNum(toIface->getWidth());
-    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm1+");\n";
-    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm1+");\n";
+    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n";
+    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm2+");\n";
   }
 
   return ret;