X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/8f0bedf735fe2b306c11c3f4a168245a05e37ccd..HEAD:/GroupBlock.cpp diff --git a/GroupBlock.cpp b/GroupBlock.cpp index 66268b9..d78a28e 100644 --- a/GroupBlock.cpp +++ b/GroupBlock.cpp @@ -6,56 +6,49 @@ #include "string.h" #include #include "Parameters.h" +#include "DelayInputModifier.h" +#include "Graph.h" int GroupBlock::counter = 1; -GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() { +GroupBlock::GroupBlock(Graph *_graph, GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock(_graph) { + parent = _parent; GroupInterface* clk = NULL; GroupInterface* rst = NULL; // force topGroup to false if this group has a parent - if (_parent != NULL) { + if (parent != NULL) { topGroup = false; name = QString("sub_group")+"_"+QString::number(counter++); - // creating clk/rst interfaces - clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock); - rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset); - addInterface(clk); - addInterface(rst); - - try { - connectClkReset(); - } - catch(Exception e) { - AbstractBlock* source = (AbstractBlock *)(e.getSource()); - cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl; - throw(e); - } } else { topGroup = true; name = QString("top_group"); // creating external clk/rst interfaces - clk = new GroupInterface(this,"ext_clk", AbstractInterface::Input, AbstractInterface::Clock); - rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset); - addInterface(clk); - addInterface(rst); - // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library } - parent = _parent; - if (_parent != NULL) { - try { - connectClkReset(); + if (createIfaces) { + if (topGroup) { + clk = new GroupInterface(this,"ext_clk_0", AbstractInterface::Input, AbstractInterface::Clock); + rst = new GroupInterface(this,"ext_reset_0", AbstractInterface::Input, AbstractInterface::Reset); + addInterface(clk); + addInterface(rst); } - catch(Exception e) { - AbstractBlock* source = (AbstractBlock *)(e.getSource()); - cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl; - throw(e); + else { + // get all clock and reset from parent + QList lstClk = parent->getInterfaces(AbstractInterface::Input, AbstractInterface::Clock); + QList lstRst = parent->getInterfaces(AbstractInterface::Input, AbstractInterface::Reset); + foreach(AbstractInterface* iface, lstClk) { + clk = new GroupInterface(this,iface->getName(),AbstractInterface::Input, AbstractInterface::Clock); + addInterface(clk); + } + foreach(AbstractInterface* iface, lstRst) { + rst = new GroupInterface(this,iface->getName(),AbstractInterface::Input, AbstractInterface::Reset); + addInterface(rst); + } } } - } GroupBlock::~GroupBlock() { @@ -147,11 +140,11 @@ void GroupBlock::createInputPattern() { } void GroupBlock::computeAdmittanceDelays() throw(Exception) { - throw(Exception(INVALID_GROUPBLOCK_USE)); + throw(Exception(INVALID_GROUPBLOCK_USE,this)); } void GroupBlock::checkInputPatternCompatibility() throw(Exception){ - throw(Exception(INVALID_GROUPBLOCK_USE)); + throw(Exception(INVALID_GROUPBLOCK_USE,this)); } @@ -175,7 +168,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { bool addIt = false; // if a block is a generator and has control outputs, add it - if (block->isGeneratorBlock()) { + if (block->isSourceBlock()) { if (block->getControlOutputs().size() > 0) addIt = true; } else { @@ -208,12 +201,10 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { while (!fifo.isEmpty()) { AbstractBlock* block = fifo.takeFirst(); - if (block->getPatternComputed()) continue; // block has already been processed - - cout << "computing compat and output for " << qPrintable(block->getName()) << endl; - + if (block->getOutputPatternComputed()) continue; // block has already been processed try { + cout << "computing compatibility of " << qPrintable(block->getName()) << endl; block->checkInputPatternCompatibility(); } catch(Exception e) { @@ -222,6 +213,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { } try { + cout << "computing output of " << qPrintable(block->getName()) << endl; block->computeOutputPattern(); } catch(Exception e) { @@ -229,7 +221,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { throw(e); } canCompute = true; - block->setPatternComputed(true); + /* add other blocks connected from block to the fifo but only if all their connected inputs are connected to blocks that have a traversalLevel >=0 @@ -238,29 +230,32 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { ConnectedInterface* conn = (ConnectedInterface*)iface; foreach(ConnectedInterface* connTo, conn->getConnectedTo()) { - AbstractBlock* block1 = connTo->getOwner(); - cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl; - bool addIt = true; - int maxLevel = 0; - - foreach(AbstractInterface* iface, block1->getControlInputs()) { - //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl; - ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); - //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl; - - if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) { - addIt = false; - break; - } - else { - if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel(); + AbstractBlock* blockTo = connTo->getOwner(); + // do sthg only if blockTo is not this group block + if (blockTo != this) { + cout << "testing if " << qPrintable(blockTo->getName()) << " has all connected inputs connected to already processed blocks" << endl; + bool addIt = true; + int maxLevel = 0; + + foreach(AbstractInterface* iface, blockTo->getControlInputs()) { + cout << qPrintable(iface->getName()) << "/" << qPrintable(iface->getOwner()->getName()) << " connected from "; + ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); + cout << qPrintable(connFrom->getName()) << "/" << qPrintable(connFrom->getOwner()->getName()) << endl; + + if ((connFrom != NULL) && (connFrom->getOwner()->getOutputPatternComputed() == false)) { + addIt = false; + break; + } + else { + if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel(); + } } - } - if (addIt) { - cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl; - block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated - fifo.append(block1); + if (addIt) { + cout << "adding " << qPrintable(blockTo->getName()) << " to the FIFO" << endl; + blockTo->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated + fifo.append(blockTo); + } } } } @@ -272,15 +267,24 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { QList* pattern = new QList(*(connIface->getConnectedFrom()->getOutputPattern())); connIface->setOutputPattern(pattern); } - setPatternComputed(true); + setOutputPatternComputed(true); } } +QList GroupBlock::getExternalResources() { + + QList list; + foreach(AbstractBlock* block, blocks) { + list.append(block->getExternalResources()); + } + return list; +} + void GroupBlock::generateVHDL(const QString& path) throw(Exception) { QString coreFile = ""; - coreFile = path; + coreFile = path; coreFile.append(Parameters::normalizeName(name)); coreFile.append(".vhd"); @@ -299,6 +303,10 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) { generateLibraries(outCore,dummyElt); generateEntity(outCore); generateArchitecture(outCore,dummyElt); + + foreach(AbstractBlock* block, blocks) { + block->generateVHDL(path); + } } catch(Exception err) { throw(err); @@ -429,6 +437,38 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( out << "architecture rtl of " << name << " is " << endl << endl; + // generate type for delays, if needed. + QList modWidth; + foreach(AbstractBlock* block, blocks) { + QList listCtlInputs = block->getControlInputs(); + foreach(AbstractInterface* iface, listCtlInputs) { + ConnectedInterface* connCtlIface = AI_TO_CON(iface); + AbstractInputModifier* modifier = connCtlIface->getInputModifier(); + if (modifier != NULL) { + ConnectedInterface* connIface = AI_TO_CON(connCtlIface->getAssociatedIface()); + int w = connIface->getWidth(); + if (w == -1) throw(Exception(INVALID_VALUE)); + if (!modWidth.contains(w)) { + modWidth.append(w); + } + } + } + } + if (modWidth.size() > 0) { + + out << " -- types for modified inputs" << endl; + out << " type vector_of_std_logic is array (natural range <>) of std_logic;" << endl; + foreach(int w, modWidth) { + QString mw = ""; + mw.setNum(w); + QString mwm1 = ""; + mwm1.setNum(w-1); + out << " type vector_of_std_logic_vector"<< mw << " is array (natural range <>) of std_logic_vector(" << mwm1 << " downto 0);" << endl; + } + out << endl; + } + + // generate the components foreach(AbstractBlock* block, blocks) { try { @@ -442,10 +482,23 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( out << endl; // generate signals out << " ----------------------------" << endl; - out << " SIGNALS" << endl; + out << " -- SIGNALS" << endl; out << " ----------------------------" << endl << endl; + // if this is top group, signals to synchronize inputs + if (topGroup) { + out << " -- signals to synchronize inputs" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + QString name = iface->toVHDL(AbstractInterface::Signal,0); + name.replace(" : ","_sync : "); + out << " signal " << name<< endl; + } + } + out << endl; + } + // "normal" signals foreach(AbstractBlock* block, blocks) { try { out << " -- signals from output ports of " << block->getName() << endl; @@ -454,7 +507,7 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl; } - else if (block->getName() == "clkrstgen") { + else if (block->getName().startsWith("clkrstgen")) { if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) { out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl; } @@ -466,12 +519,24 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } out << endl; } + + // signal for modifiers foreach(AbstractBlock* block, blocks) { - try { - out << " -- signals for modified input ports of " << block->getName() << endl; - QList listInputs = block->getInputs(); - foreach(AbstractInterface* iface, listInputs) { - if (iface->getPurpose() == AbstractInterface::Control) { + bool hasModif = false; + QList listCtlInputs = block->getControlInputs(); + + foreach(AbstractInterface* iface, listCtlInputs) { + ConnectedInterface* connCtlIface = AI_TO_CON(iface); + AbstractInputModifier* modifier = connCtlIface->getInputModifier(); + if (modifier != NULL) { + hasModif = true; + break; + } + } + if (hasModif) { + try { + out << " -- signals for modified input ports of " << block->getName() << endl; + foreach(AbstractInterface* iface, listCtlInputs) { ConnectedInterface* connCtlIface = AI_TO_CON(iface); AbstractInputModifier* modifier = connCtlIface->getInputModifier(); if (modifier != NULL) { @@ -479,11 +544,11 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } } } + catch(Exception e) { + throw(e); + } + out << endl; } - catch(Exception e) { - throw(e); - } - out << endl; } out << "begin" << endl; @@ -552,7 +617,12 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } } else if (fromIface->isGroupInterface()) { - portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n"; + if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) { + portMap += " " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n"; + } + else { + portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n"; + } } } if (listOutputs.size()>0) { @@ -600,6 +670,57 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } } + if (topGroup) { + // generate input sync process for each clock domain + out << " -- process to synchronize inputs of top group" << endl; + for(int i=0;igetClocks().size();i++) { + // check if there are some inputs that must be sync with clock domain i + bool mustSync = false; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + mustSync = true; + break; + } + } + } + if (mustSync) { + out << "sync_inputs_" << i << " : process(from_clkrstgen_" << i << "_clk,from_clkrstgen_" << i << "_reset)" << endl; + out << " begin" << endl; + out << " if from_clkrstgen_" << i << "_reset = '1' then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl; + } + } + } + } + out << " elsif rising_edge(from_clkrstgen_" << i << "_clk) then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + } + } + } + out << " end if;" << endl; + out << " end process sync_inputs_" << i << ";" << endl; + + out << endl; + } + } + } + out << "end architecture rtl;" << endl; }