X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/8fb3c55ee009a11db5e1c08a4cfb286979412745..HEAD:/GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index d682a57..d78a28e 100644
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -7,10 +7,11 @@
 #include <sstream>
 #include "Parameters.h"
 #include "DelayInputModifier.h"
+#include "Graph.h"
 
 int GroupBlock::counter = 1;
 
-GroupBlock::GroupBlock(GroupBlock *_parent, bool createIfaces) throw(Exception) :  AbstractBlock() {
+GroupBlock::GroupBlock(Graph *_graph, GroupBlock *_parent, bool createIfaces) throw(Exception) :  AbstractBlock(_graph) {
 
   parent = _parent;
   GroupInterface* clk = NULL;
@@ -200,12 +201,10 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
   while (!fifo.isEmpty()) {
     AbstractBlock* block = fifo.takeFirst();
     
-    if (block->getOutputPatternComputed()) continue; // block has already been processed
-
-    cout << "computing compat and output for " << qPrintable(block->getName()) << endl;
-    
+    if (block->getOutputPatternComputed()) continue; // block has already been processed    
 
     try {
+      cout << "computing compatibility of " << qPrintable(block->getName()) << endl;
       block->checkInputPatternCompatibility();
     }
     catch(Exception e) {      
@@ -214,6 +213,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
     }   
     
     try {
+      cout << "computing output of " << qPrintable(block->getName()) << endl;
       block->computeOutputPattern();
     }
     catch(Exception e) {
@@ -230,29 +230,32 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
       ConnectedInterface* conn = (ConnectedInterface*)iface;
       foreach(ConnectedInterface* connTo, conn->getConnectedTo()) {
 
-        AbstractBlock* block1 = connTo->getOwner();
-        cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl;
-        bool addIt = true;
-        int maxLevel = 0;
-
-        foreach(AbstractInterface* iface, block1->getControlInputs()) {
-          //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
-          ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
-          //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
-
-          if ((connFrom != NULL) && (connFrom->getOwner()->getOutputPatternComputed() == false)) {
-            addIt = false;
-            break;
-          }
-          else {
-            if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel();
+        AbstractBlock* blockTo = connTo->getOwner();
+        // do sthg only if blockTo is not this group block
+        if (blockTo != this) {
+          cout << "testing if " << qPrintable(blockTo->getName()) << " has all connected inputs connected to already processed blocks" << endl;
+          bool addIt = true;
+          int maxLevel = 0;
+
+          foreach(AbstractInterface* iface, blockTo->getControlInputs()) {
+            cout << qPrintable(iface->getName()) << "/" << qPrintable(iface->getOwner()->getName()) << " connected from ";
+            ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+            cout << qPrintable(connFrom->getName()) << "/" << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+            if ((connFrom != NULL) && (connFrom->getOwner()->getOutputPatternComputed() == false)) {
+              addIt = false;
+              break;
+            }
+            else {
+              if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel();
+            }
           }
-        }
 
-        if (addIt) {
-          cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl;
-          block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated
-          fifo.append(block1);
+          if (addIt) {
+            cout << "adding " << qPrintable(blockTo->getName()) << " to the FIFO" << endl;
+            blockTo->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated
+            fifo.append(blockTo);
+          }
         }
       }
     }
@@ -482,16 +485,18 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << "  --  SIGNALS" << endl;
   out << "  ----------------------------" << endl << endl;
 
-  // signals to synchronize inputs
-  out << "  -- signals to synchronize inputs" << endl;
-  foreach(AbstractInterface* iface, getInputs()) {
-    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-      QString name = iface->toVHDL(AbstractInterface::Signal,0);
-      name.replace(" : ","_sync : ");
-      out << "  signal " << name<< endl;
+  // if this is top group, signals to synchronize inputs
+  if (topGroup) {
+    out << "  -- signals to synchronize inputs" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        QString name = iface->toVHDL(AbstractInterface::Signal,0);
+        name.replace(" : ","_sync : ");
+        out << "  signal " << name<< endl;
+      }
     }
+    out << endl;
   }
-  out << endl;
 
   // "normal" signals
   foreach(AbstractBlock* block, blocks) {
@@ -502,7 +507,7 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
         if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
           out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
         }
-        else if (block->getName() == "clkrstgen") {
+        else if (block->getName().startsWith("clkrstgen")) {
           if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
             out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
           }
@@ -666,36 +671,54 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   }
 
   if (topGroup) {
-    // generate input sync process
+    // generate input sync process for each clock domain
     out << "  -- process to synchronize inputs of top group" << endl;
-    out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
-    out << "  begin" << endl;
-    out << "    if from_clkrstgen_reset = '1' then" << endl;
-    foreach(AbstractInterface* iface, getInputs()) {
-      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-        if (iface->getWidth() == 0) {
-          out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
-        }
-        else {
-          out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+    for(int i=0;i<graph->getClocks().size();i++) {
+      // check if there are some inputs that must be sync with clock domain i
+      bool mustSync = false;
+      foreach(AbstractInterface* iface, getInputs()) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          if (iface->getClockDomain() == i) {
+            mustSync = true;
+            break;
+          }
         }
       }
-    }
-    out << "    elsif rising_edge(from_clkrstgen_clk) then" << endl;
-    foreach(AbstractInterface* iface, getInputs()) {
-      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-        if (iface->getWidth() == 0) {
-          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+      if (mustSync) {
+        out << "sync_inputs_" << i << " : process(from_clkrstgen_" << i << "_clk,from_clkrstgen_" << i << "_reset)" << endl;
+        out << "  begin" << endl;
+        out << "    if from_clkrstgen_" << i << "_reset = '1' then" << endl;
+        foreach(AbstractInterface* iface, getInputs()) {
+          if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+            if (iface->getClockDomain() == i) {
+              if (iface->getWidth() == 0) {
+                out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+              }
+              else {
+                out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+              }
+            }
+          }
         }
-        else {
-          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        out << "    elsif rising_edge(from_clkrstgen_" << i << "_clk) then" << endl;
+        foreach(AbstractInterface* iface, getInputs()) {
+          if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+            if (iface->getClockDomain() == i) {
+              if (iface->getWidth() == 0) {
+                out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+              }
+              else {
+                out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+              }
+            }
+          }
         }
+        out << "    end if;" << endl;
+        out << "  end process sync_inputs_" << i << ";" << endl;
+
+        out << endl;
       }
     }
-    out << "    end if;" << endl;
-    out << "  end process sync_inputs;" << endl;
-
-    out << endl;
   }
 
   out << "end architecture rtl;" << endl;