X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/a13795fc34cd1e74f94695d35253c3d00abec9bc..4327c2b8817b627249d98d889835726217c81a4e:/AbstractBlock.h

diff --git a/AbstractBlock.h b/AbstractBlock.h
index fad9b53..efbd474 100644
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -86,9 +86,7 @@ public:
    * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces
    * \param idBlockClk is the id of the clock interface (there may be severals)
    * \param idGen is the id of the clkrstgen block
-  */
-  void connectClock(QString clkName, int idGen = 0) throw(Exception);
-  void connectReset(QString rstName, int idGen = 0) throw(Exception);
+  */  
   virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation
   virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code
   void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference