X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/a13795fc34cd1e74f94695d35253c3d00abec9bc..HEAD:/AbstractBlock.h

diff --git a/AbstractBlock.h b/AbstractBlock.h
index fad9b53..f40af86 100644
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -75,7 +75,7 @@ public:
   virtual bool isGroupBlock();
   virtual bool isStimuliBlock(); //! a stimuli block is outside the top group and simulates a peripheral (NB: this is also a source)
   virtual bool isTopGroupBlock();
-  bool isSourceBlock(); //! a source block has no data inputs and thus executes infinitely
+  bool isSourceBlock(); //! a source block is either a block that has no data inputs or that is of special type source. Thus it executes infinitely
   bool isSinkBlock(); //! a sink block has no data outputs and just collects what it receives (i.e. no compatibility check)
   bool isWBConfigurable();
 
@@ -86,9 +86,7 @@ public:
    * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces
    * \param idBlockClk is the id of the clock interface (there may be severals)
    * \param idGen is the id of the clkrstgen block
-  */
-  void connectClock(QString clkName, int idGen = 0) throw(Exception);
-  void connectReset(QString rstName, int idGen = 0) throw(Exception);
+  */  
   virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation
   virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code
   void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference