X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/bc5d59217a24b25c1b913bec4a41dd026d02720c..refs/heads/master:/GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index d3ff0ed..d78a28e 100644
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -7,6 +7,7 @@
 #include <sstream>
 #include "Parameters.h"
 #include "DelayInputModifier.h"
+#include "Graph.h"
 
 int GroupBlock::counter = 1;
 
@@ -484,16 +485,18 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << "  --  SIGNALS" << endl;
   out << "  ----------------------------" << endl << endl;
 
-  // signals to synchronize inputs
-  out << "  -- signals to synchronize inputs" << endl;
-  foreach(AbstractInterface* iface, getInputs()) {
-    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-      QString name = iface->toVHDL(AbstractInterface::Signal,0);
-      name.replace(" : ","_sync : ");
-      out << "  signal " << name<< endl;
+  // if this is top group, signals to synchronize inputs
+  if (topGroup) {
+    out << "  -- signals to synchronize inputs" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        QString name = iface->toVHDL(AbstractInterface::Signal,0);
+        name.replace(" : ","_sync : ");
+        out << "  signal " << name<< endl;
+      }
     }
+    out << endl;
   }
-  out << endl;
 
   // "normal" signals
   foreach(AbstractBlock* block, blocks) {
@@ -504,7 +507,7 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
         if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
           out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
         }
-        else if (block->getName() == "clkrstgen") {
+        else if (block->getName().startsWith("clkrstgen")) {
           if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
             out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
           }
@@ -668,36 +671,54 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   }
 
   if (topGroup) {
-    // generate input sync process
+    // generate input sync process for each clock domain
     out << "  -- process to synchronize inputs of top group" << endl;
-    out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
-    out << "  begin" << endl;
-    out << "    if from_clkrstgen_reset = '1' then" << endl;
-    foreach(AbstractInterface* iface, getInputs()) {
-      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-        if (iface->getWidth() == 0) {
-          out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
-        }
-        else {
-          out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+    for(int i=0;i<graph->getClocks().size();i++) {
+      // check if there are some inputs that must be sync with clock domain i
+      bool mustSync = false;
+      foreach(AbstractInterface* iface, getInputs()) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          if (iface->getClockDomain() == i) {
+            mustSync = true;
+            break;
+          }
         }
       }
-    }
-    out << "    elsif rising_edge(from_clkrstgen_clk) then" << endl;
-    foreach(AbstractInterface* iface, getInputs()) {
-      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-        if (iface->getWidth() == 0) {
-          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+      if (mustSync) {
+        out << "sync_inputs_" << i << " : process(from_clkrstgen_" << i << "_clk,from_clkrstgen_" << i << "_reset)" << endl;
+        out << "  begin" << endl;
+        out << "    if from_clkrstgen_" << i << "_reset = '1' then" << endl;
+        foreach(AbstractInterface* iface, getInputs()) {
+          if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+            if (iface->getClockDomain() == i) {
+              if (iface->getWidth() == 0) {
+                out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+              }
+              else {
+                out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+              }
+            }
+          }
         }
-        else {
-          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        out << "    elsif rising_edge(from_clkrstgen_" << i << "_clk) then" << endl;
+        foreach(AbstractInterface* iface, getInputs()) {
+          if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+            if (iface->getClockDomain() == i) {
+              if (iface->getWidth() == 0) {
+                out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+              }
+              else {
+                out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+              }
+            }
+          }
         }
+        out << "    end if;" << endl;
+        out << "  end process sync_inputs_" << i << ";" << endl;
+
+        out << endl;
       }
     }
-    out << "    end if;" << endl;
-    out << "  end process sync_inputs;" << endl;
-
-    out << endl;
   }
 
   out << "end architecture rtl;" << endl;