X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/cfe8322b50c9ef08ffbc3e52b0849bca4cd1d0bf..9bfa0c13066918f440ac2b5461fb3f8847f43fd6:/GroupBlock.cpp?ds=sidebyside

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 716cea6..f618789 100644
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -1,27 +1,52 @@
 #include "GroupBlock.h"
 #include "BlockParameterGeneric.h"
 #include "AbstractInterface.h"
+#include "ConnectedInterface.h"
+#include "GroupInterface.h"
 #include "string.h"
 #include <sstream>
+#include "Parameters.h"
 
 int GroupBlock::counter = 1;
 
 GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) :  AbstractBlock() {
 
+  GroupInterface* clk = NULL;
+  GroupInterface* rst = NULL;
+  
   // force topGroup to false if this group has a parent
-  if (_parent != NULL) {    
+  if (_parent != NULL) {
     topGroup = false;
     name = QString("sub_group")+"_"+QString::number(counter++);
+    // creating clk/rst interfaces
+    clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
+    rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
+    addInterface(clk);
+    addInterface(rst);    
   }
   else {
     topGroup = true;
     name = QString("top_group");
+    // creating external clk/rst interfaces
+    clk = new GroupInterface(this,"ext_clk", AbstractInterface::Input, AbstractInterface::Clock);
+    rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset);
+    addInterface(clk);
+    addInterface(rst);
+    // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library
   }
   parent = _parent;
-  if (parent != NULL) {
-    // adding this to the child blocks of parent
-    AB_TO_GRP(parent)->addBlock(this);
+
+  if (_parent != NULL) {
+    try {
+      connectClkReset();
+    }
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);
+    }
   }
+
 }
 
 GroupBlock::~GroupBlock() {
@@ -104,19 +129,296 @@ void GroupBlock::removeGenericParameter(QString name) {
   if (p != NULL) params.removeAll(p);
 }
 
-void GroupBlock::initInputPattern() {
+void GroupBlock::createInputPattern() {
   foreach(AbstractInterface* iface, getControlInputs()) {
-    iface->setOutputPattern(iface->getConnectedFrom()->getOutputPattern());    
-  }  
+    ConnectedInterface* connIface = AI_TO_CON(iface);
+    QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
+    connIface->setOutputPattern(pattern);
+  }
+}
+
+void GroupBlock::computeAdmittanceDelays() throw(Exception) {
+  throw(Exception(INVALID_GROUPBLOCK_USE));
 }
 
-void GroupBlock::computeOutputPattern(int nbExec) {
+void GroupBlock::checkInputPatternCompatibility()  throw(Exception){
+  throw(Exception(INVALID_GROUPBLOCK_USE));
+}
+
+
+void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
+
+  static QString fctName = "GroupBlock::computeOutputPattern()";
+#ifdef DEBUG_FCTNAME
+  cout << "call to " << qPrintable(fctName) << endl;
+#endif
+
+  cout << "computing output pattern of group " << qPrintable(name) << endl;
   
+  bool canCompute = false;
   // get the input pattern on each inputs
-  initInputPattern();
-  // find blocks that are connected to that inputs
+  createInputPattern();
+  
+  cout << "Input pattern OK" << endl;
+  // find blocks that are connected to that inputs and generators
+  QList<AbstractBlock*> fifo;
+  foreach(AbstractBlock* block, blocks) {
+
+    bool addIt = false;
+    // if a block is a generator and has control outputs, add it
+    if (block->isGeneratorBlock()) {
+      if (block->getControlOutputs().size() > 0) addIt = true;
+    }
+    else {
+      // if the block has all its connected control inputs that are connected to an intput of the group, add it too
+      if (block->getControlInputs().size() > 0) {
+        addIt = true;
+        foreach(AbstractInterface* iface, block->getControlInputs()) {
+          //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+          ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+          //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+          if (connFrom == NULL) {
+            addIt = false;
+            break;
+          }
+          else if (connFrom->getOwner() != this) {
+            addIt = false;
+            break;
+          }
+        }
+      }
+    }
+    if (addIt) {
+      cout << "adding " << qPrintable(block->getName()) << " to initialize the FIFO" << endl;
+      block->setTraversalLevel(0); // level 0 = first blocks to be evaluated
+      fifo.append(block);
+    }
+  }
   
-  foreach(AbstractInterface* iface, getControlOutputs()) {
-    iface->setOutputPattern(iface->getConnectedFrom()->getOutputPattern());    
+  while (!fifo.isEmpty()) {
+    AbstractBlock* block = fifo.takeFirst();
+    
+    if (block->getPatternComputed()) continue; // block has already been processed
+
+    cout << "computing compat and output for " << qPrintable(block->getName()) << endl;
+    
+
+    try {
+      block->checkInputPatternCompatibility();
+    }
+    catch(Exception e) {      
+      cout << qPrintable(block->getName()) << " is not compatible with its input pattern" << endl;
+      throw(e);
+    }   
+    
+    try {
+      block->computeOutputPattern();
+    }
+    catch(Exception e) {
+      cout << "cannot finalize output pattern computation of " << qPrintable(block->getName()) << endl;
+      throw(e);
+    }
+    canCompute = true;
+    block->setPatternComputed(true);
+    /* add other blocks connected from block to the fifo but only if
+       all their connected inputs are connected to blocks that have
+       a traversalLevel >=0
+     */
+    foreach(AbstractInterface* iface, block->getControlOutputs()) {
+      ConnectedInterface* conn = (ConnectedInterface*)iface;
+      foreach(ConnectedInterface* connTo, conn->getConnectedTo()) {
+
+        AbstractBlock* block1 = connTo->getOwner();
+        cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl;
+        bool addIt = true;
+        int maxLevel = 0;
+
+        foreach(AbstractInterface* iface, block1->getControlInputs()) {
+          //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+          ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+          //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+          if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) {
+            addIt = false;
+            break;
+          }
+          else {
+            if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel();
+          }
+        }
+
+        if (addIt) {
+          cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl;
+          block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated
+          fifo.append(block1);
+        }
+      }
+    }
+  }
+
+  if (canCompute) {
+    foreach(AbstractInterface* iface, getControlOutputs()) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
+      connIface->setOutputPattern(pattern);
+    }
+    setPatternComputed(true);
   }
 }
+
+void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
+
+  QString coreFile = "";
+
+  coreFile = path;
+  coreFile.append(Parameters::normalizeName(name));
+  coreFile.append(".vhd");
+
+  QFile vhdlCore(coreFile);
+
+  if (!vhdlCore.open(QIODevice::WriteOnly)) {
+    throw(Exception(VHDLFILE_NOACCESS));
+  }
+
+  cout << "generate VHDL of block " << qPrintable(name) << " in " << qPrintable(coreFile) << endl;
+  QTextStream outCore(&vhdlCore);
+
+  QDomElement dummyElt;
+  try {
+    generateComments(outCore,dummyElt,"");
+    generateLibraries(outCore,dummyElt);
+    generateEntity(outCore);
+    generateArchitecture(outCore,dummyElt);
+  }
+  catch(Exception err) {
+    throw(err);
+  }
+
+  vhdlCore.close();
+}
+
+
+void GroupBlock::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) {
+  out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
+}
+
+void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) {
+
+  out << "library IEEE;" << endl;
+  out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+  out << "use IEEE.numeric_std.all;" << endl;
+
+}
+
+void GroupBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {
+
+  int i;
+
+  out << "entity " << name << " is " << endl;
+
+  QList<BlockParameter*> listGenerics = getGenericParameters();
+  QList<AbstractInterface*> listInputs = getInputs();
+  QList<AbstractInterface*> listOutputs = getOutputs();
+  QList<AbstractInterface*> listBidirs = getBidirs();
+
+  if (!listGenerics.isEmpty()) {
+    out << "  generic (" << endl;
+    for(i=0;i<listGenerics.size()-1;i++) {
+      out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+    }
+    out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << "    );" << endl;
+  }
+
+  out << "  port (" << endl;
+
+  // Generation of the clk & rst signals
+  out << "    -- clk/rst" << endl;
+  foreach(AbstractInterface* iface, listInputs) {
+    if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
+      out << "    " << iface->getName() << " : in std_logic;" << endl;
+    }
+  }
+
+  int count = 0;
+  foreach(AbstractInterface* iface, getInterfaces()) {
+    if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;
+  }
+  // Generation of the data/control signals
+
+  int flag = 0;
+  bool first = true;
+
+  foreach(AbstractInterface* iface, listInputs) {
+    if(iface->getPurpose() == AbstractInterface::Data) {
+      if (first) {
+        out << "    -- input data ports" << endl;
+        first = false;
+      }
+      count--;
+      if (count == 0) flag = AbstractInterface::NoComma;
+      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+    }
+  }
+  first = true;
+  foreach(AbstractInterface* iface, listInputs) {
+    if(iface->getPurpose() == AbstractInterface::Control) {
+      if (first) {
+        out << "    -- input control ports" << endl;
+        first = false;
+      }
+      count--;
+      if (count == 0) flag = AbstractInterface::NoComma;
+      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+    }
+  }
+  first = true;
+  foreach(AbstractInterface* iface, listOutputs) {
+    if(iface->getPurpose() == AbstractInterface::Data) {
+      if (first) {
+        out << "    -- output data ports" << endl;
+        first = false;
+      }
+      count--;
+      if (count == 0) flag = AbstractInterface::NoComma;
+      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+    }
+  }
+  first = true;
+  foreach(AbstractInterface* iface, listOutputs) {
+    if(iface->getPurpose() == AbstractInterface::Control) {
+      if (first) {
+        out << "    -- output control ports" << endl;
+        first = false;
+      }
+      count--;
+      if (count == 0) flag = AbstractInterface::NoComma;
+      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+    }
+  }
+  first = true;
+  foreach(AbstractInterface* iface, listBidirs) {
+    if(iface->getPurpose() == AbstractInterface::Data) {
+      if (first) {
+        out << "    -- bidirs data ports" << endl;
+        first = false;
+      }
+      count--;
+      if (count == 0) flag = AbstractInterface::NoComma;
+      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+    }
+  }
+  out << "    );" << endl << endl;
+  out << "end " << name << ";" << endl << endl;
+
+}
+
+void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {
+
+}
+
+void GroupBlock::generateController(QTextStream &out) throw(Exception) {
+  
+}
+