X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/e40a5399ec7887c2606f18575c809b0d05b09278..3fb762e7042d9b4a1cf78556ad9ed7f117cc53ba:/lib/references/clkdomain_convert_1024x8.xml?ds=inline

diff --git a/lib/references/clkdomain_convert_1024x8.xml b/lib/references/clkdomain_convert_1024x8.xml
index 1df9cf1..b6e19c4 100644
--- a/lib/references/clkdomain_convert_1024x8.xml
+++ b/lib/references/clkdomain_convert_1024x8.xml
@@ -1,12 +1,10 @@
 <!DOCTYPE clkdomain_convert_1024x8>
-<block version="0.1">
+<block version="0.1" special="clkconvert">
   <informations>
     <name>clkdomain_convert_1024x8</name>
     <category ids="10"/>
     <description>
-      <brief>This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.
-</brief>
-      <detailed>This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.</detailed>
+      This IP allows to pass 8 bits values from a clock domain to another. It uses a FIFO of 1024 entries.
     </description>
   </informations>
   <parameters>
@@ -15,14 +13,14 @@
   </parameters>
   <interfaces>
     <inputs>
-      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_rd" purpose="clock"/>
-      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_wr" purpose="clock"/>
+      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_in" purpose="clock"/>
+      <input width="1" multiplicity="1" endian="little" type="boolean" name="clk_out" purpose="clock"/>
       <input width="1" multiplicity="1" endian="little" type="boolean" name="reset" purpose="reset"/>
-      <input width="8" multiplicity="1" endian="little" type="natural" name="data_in" purpose="data" clock="clk_rd"/>
+      <input width="8" multiplicity="1" endian="little" type="natural" name="data_in" purpose="data" clock="clk_in"/>
       <control iface="data_in"/>
     </inputs>
     <outputs>
-      <output width="8" multiplicity="1" endian="little" type="natural" name="data_out" purpose="data" clock="clk_wr"/>
+      <output width="8" multiplicity="1" endian="little" type="natural" name="data_out" purpose="data" clock="clk_out"/>
       <control iface="data_out"/>
     </outputs>
   </interfaces>