X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/blobdiff_plain/e40a5399ec7887c2606f18575c809b0d05b09278..HEAD:/GroupBlock.cpp?ds=inline diff --git a/GroupBlock.cpp b/GroupBlock.cpp index fda0546..d78a28e 100644 --- a/GroupBlock.cpp +++ b/GroupBlock.cpp @@ -7,10 +7,11 @@ #include #include "Parameters.h" #include "DelayInputModifier.h" +#include "Graph.h" int GroupBlock::counter = 1; -GroupBlock::GroupBlock(GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock() { +GroupBlock::GroupBlock(Graph *_graph, GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock(_graph) { parent = _parent; GroupInterface* clk = NULL; @@ -139,11 +140,11 @@ void GroupBlock::createInputPattern() { } void GroupBlock::computeAdmittanceDelays() throw(Exception) { - throw(Exception(INVALID_GROUPBLOCK_USE)); + throw(Exception(INVALID_GROUPBLOCK_USE,this)); } void GroupBlock::checkInputPatternCompatibility() throw(Exception){ - throw(Exception(INVALID_GROUPBLOCK_USE)); + throw(Exception(INVALID_GROUPBLOCK_USE,this)); } @@ -167,7 +168,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { bool addIt = false; // if a block is a generator and has control outputs, add it - if (block->isGeneratorBlock()) { + if (block->isSourceBlock()) { if (block->getControlOutputs().size() > 0) addIt = true; } else { @@ -200,12 +201,10 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { while (!fifo.isEmpty()) { AbstractBlock* block = fifo.takeFirst(); - if (block->getPatternComputed()) continue; // block has already been processed - - cout << "computing compat and output for " << qPrintable(block->getName()) << endl; - + if (block->getOutputPatternComputed()) continue; // block has already been processed try { + cout << "computing compatibility of " << qPrintable(block->getName()) << endl; block->checkInputPatternCompatibility(); } catch(Exception e) { @@ -214,6 +213,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { } try { + cout << "computing output of " << qPrintable(block->getName()) << endl; block->computeOutputPattern(); } catch(Exception e) { @@ -221,7 +221,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { throw(e); } canCompute = true; - block->setPatternComputed(true); + /* add other blocks connected from block to the fifo but only if all their connected inputs are connected to blocks that have a traversalLevel >=0 @@ -230,29 +230,32 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { ConnectedInterface* conn = (ConnectedInterface*)iface; foreach(ConnectedInterface* connTo, conn->getConnectedTo()) { - AbstractBlock* block1 = connTo->getOwner(); - cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl; - bool addIt = true; - int maxLevel = 0; - - foreach(AbstractInterface* iface, block1->getControlInputs()) { - //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl; - ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); - //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl; - - if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) { - addIt = false; - break; - } - else { - if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel(); + AbstractBlock* blockTo = connTo->getOwner(); + // do sthg only if blockTo is not this group block + if (blockTo != this) { + cout << "testing if " << qPrintable(blockTo->getName()) << " has all connected inputs connected to already processed blocks" << endl; + bool addIt = true; + int maxLevel = 0; + + foreach(AbstractInterface* iface, blockTo->getControlInputs()) { + cout << qPrintable(iface->getName()) << "/" << qPrintable(iface->getOwner()->getName()) << " connected from "; + ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom(); + cout << qPrintable(connFrom->getName()) << "/" << qPrintable(connFrom->getOwner()->getName()) << endl; + + if ((connFrom != NULL) && (connFrom->getOwner()->getOutputPatternComputed() == false)) { + addIt = false; + break; + } + else { + if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel(); + } } - } - if (addIt) { - cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl; - block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated - fifo.append(block1); + if (addIt) { + cout << "adding " << qPrintable(blockTo->getName()) << " to the FIFO" << endl; + blockTo->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated + fifo.append(blockTo); + } } } } @@ -264,7 +267,7 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) { QList* pattern = new QList(*(connIface->getConnectedFrom()->getOutputPattern())); connIface->setOutputPattern(pattern); } - setPatternComputed(true); + setOutputPatternComputed(true); } } @@ -482,16 +485,18 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( out << " -- SIGNALS" << endl; out << " ----------------------------" << endl << endl; - // signals to synchronize inputs - out << " -- signals to synchronize inputs" << endl; - foreach(AbstractInterface* iface, getInputs()) { - if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { - QString name = iface->toVHDL(AbstractInterface::Signal,0); - name.replace(" : ","_sync : "); - out << " signal " << name<< endl; + // if this is top group, signals to synchronize inputs + if (topGroup) { + out << " -- signals to synchronize inputs" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + QString name = iface->toVHDL(AbstractInterface::Signal,0); + name.replace(" : ","_sync : "); + out << " signal " << name<< endl; + } } + out << endl; } - out << endl; // "normal" signals foreach(AbstractBlock* block, blocks) { @@ -502,7 +507,7 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl; } - else if (block->getName() == "clkrstgen") { + else if (block->getName().startsWith("clkrstgen")) { if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) { out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl; } @@ -666,36 +671,54 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } if (topGroup) { - // generate input sync process + // generate input sync process for each clock domain out << " -- process to synchronize inputs of top group" << endl; - out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl; - out << " begin" << endl; - out << " if from_clkrstgen_reset = '1' then" << endl; - foreach(AbstractInterface* iface, getInputs()) { - if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { - if (iface->getWidth() == 0) { - out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl; - } - else { - out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl; + for(int i=0;igetClocks().size();i++) { + // check if there are some inputs that must be sync with clock domain i + bool mustSync = false; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + mustSync = true; + break; + } } } - } - out << " elsif rising_edge(from_clkrstgen_clk) then" << endl; - foreach(AbstractInterface* iface, getInputs()) { - if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { - if (iface->getWidth() == 0) { - out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + if (mustSync) { + out << "sync_inputs_" << i << " : process(from_clkrstgen_" << i << "_clk,from_clkrstgen_" << i << "_reset)" << endl; + out << " begin" << endl; + out << " if from_clkrstgen_" << i << "_reset = '1' then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl; + } + } + } } - else { - out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + out << " elsif rising_edge(from_clkrstgen_" << i << "_clk) then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getClockDomain() == i) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + } + } } + out << " end if;" << endl; + out << " end process sync_inputs_" << i << ";" << endl; + + out << endl; } } - out << " end if;" << endl; - out << " end process sync_inputs;" << endl; - - out << endl; } out << "end architecture rtl;" << endl;