From: stephane Domas Date: Fri, 6 Apr 2018 11:34:03 +0000 (+0200) Subject: finished VHDL gen X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/commitdiff_plain/6ca6321283b9c93a6df9dcd5216bfa01df9ad24b?hp=14cd6d834ab531525a51c6a6992583b3e9143e02 finished VHDL gen --- diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp index a60d7e2..db89107 100644 --- a/DelayInputModifier.cpp +++ b/DelayInputModifier.cpp @@ -29,10 +29,10 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) { ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface()); QString toName = toIface->getOwner()->getName()+"_"+toIface->getName(); QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName(); - QString dm1 = ""; QString dm2 = ""; - dm1.setNum(delayLength-1); + QString dm3 = ""; dm2.setNum(delayLength-2); + dm3.setNum(delayLength-3); QString ret=""; QString clkName = "clk"; QString resetName = "reset"; @@ -50,12 +50,12 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) { ret += " "+toName+"_mod <= (others => '0');\n"; ret += " "+toCtlName+"_mod <= '0';\n"; ret += " elsif rising_edge("+clkName+") then\n"; - ret += " "+toName+"_mod <= "+toName+"_dly("+dm1+");\n"; - ret += " "+toCtlName+"_mod <= "+toCtlName+"_dly("+dm1+");\n"; + ret += " "+toName+"_mod <= "+toName+"_dly("+dm2+");\n"; + ret += " "+toCtlName+"_mod <= "+toCtlName+"_dly("+dm2+");\n"; ret += " "+toName+"_dly(0) <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n"; ret += " "+toCtlName+"_dly(0) <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n"; - ret += " "+toName+"_dly(1 to "+dm1+") <= "+toName+"_dly(0 to "+dm2+");\n"; - ret += " "+toCtlName+"_dly(1 to "+dm1+") <= "+toCtlName+"_dly(0 to "+dm2+");\n"; + ret += " "+toName+"_dly(1 to "+dm2+") <= "+toName+"_dly(0 to "+dm3+");\n"; + ret += " "+toCtlName+"_dly(1 to "+dm2+") <= "+toCtlName+"_dly(0 to "+dm3+");\n"; ret += " end if;\n"; ret += " end process "+toName + "_mod_process;\n"; } @@ -68,8 +68,8 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) { ret += " signal "+sig+"\n"; QString wStr=""; wStr.setNum(toIface->getWidth()); - ret += " signal "+toName+"_dly : vector_of_std_logic_vector"+wStr+"(0 to "+dm1+");\n"; - ret += " signal "+toCtlName+"_dly : vector_of_std_logic(0 to "+dm1+");\n"; + ret += " signal "+toName+"_dly : vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n"; + ret += " signal "+toCtlName+"_dly : vector_of_std_logic(0 to "+dm2+");\n"; } return ret; diff --git a/Dispatcher.cpp b/Dispatcher.cpp index b9e09a9..cdf8ee3 100644 --- a/Dispatcher.cpp +++ b/Dispatcher.cpp @@ -256,11 +256,18 @@ void Dispatcher::generateVHDL() throw(Exception) { } out << endl; out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl; - out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl; + out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl; + out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl; out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl; paramFile.close(); + QString msg = "VHDL generation completed successfully. Go to "; + msg += params->projectPath+" and type the following commands to launch a simulation:\n"; + msg += "\tmake clean\n"; + msg += "\tmake\n"; + msg += "\tmake view\n"; + QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok); } diff --git a/GroupBlock.cpp b/GroupBlock.cpp index 5b4f34e..ab76563 100644 --- a/GroupBlock.cpp +++ b/GroupBlock.cpp @@ -491,7 +491,18 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( out << " -- SIGNALS" << endl; out << " ----------------------------" << endl << endl; -// "normal" signals + // signals to synchronize inputs + out << " -- signals to synchronize inputs" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + QString name = iface->toVHDL(AbstractInterface::Signal,0); + name.replace(" : ","_sync : "); + out << " signal " << name<< endl; + } + } + out << endl; + + // "normal" signals foreach(AbstractBlock* block, blocks) { try { out << " -- signals from output ports of " << block->getName() << endl; @@ -610,7 +621,12 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } } else if (fromIface->isGroupInterface()) { - portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n"; + if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) { + portMap += " " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n"; + } + else { + portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n"; + } } } if (listOutputs.size()>0) { @@ -658,6 +674,39 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw( } } + if (topGroup) { + // generate input sync process + out << " -- process to synchronize inputs of top group" << endl; + out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl; + out << " begin" << endl; + out << " if from_clkrstgen_reset = '1' then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl; + } + } + } + out << " elsif rising_edge(from_clkrstgen_clk) then" << endl; + foreach(AbstractInterface* iface, getInputs()) { + if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) { + if (iface->getWidth() == 0) { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + else { + out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl; + } + } + } + out << " end if;" << endl; + out << " end process sync_inputs;" << endl; + + out << endl; + } + out << "end architecture rtl;" << endl; } diff --git a/blast.creator.user b/blast.creator.user index 3230c1f..8cb263a 100644 --- a/blast.creator.user +++ b/blast.creator.user @@ -1,6 +1,6 @@ - + EnvironmentId diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml index e941579..055ec26 100644 --- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml +++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml @@ -33,7 +33,6 @@ signal do_sum_cr : std_logic; signal do_sum_cr_dly : std_logic; signal do_sum_cb : std_logic; signal do_sum_cb_dly : std_logic; -signal do_out : std_logic; signal do_out_cr : std_logic; signal do_out_cb : std_logic; signal do_out_y : std_logic; @@ -69,8 +68,6 @@ signal a_cb : std_logic_vector(17 downto 0); signal b_cb : std_logic_vector(17 downto 0); signal s_cb : std_logic_vector(47 downto 0); -signal compo_out : std_logic_vector(7 downto 0); - begin y_multiplier : mult_accum @@ -156,7 +153,8 @@ end process multy_process; sumy_process : process (@{clk}, @{reset}) begin if @{reset} = '1' then -bypass_y <= '0'; +bypass_y <= '1'; +do_sum_y_dly <= '0'; y <= to_signed(0, 9); y_dly1 <= to_signed(0, 9); y_dly2 <= to_signed(0, 9); @@ -215,7 +213,8 @@ end process multcb_process; sumcb_process : process (@{clk}, @{reset}) begin if @{reset} = '1' then -bypass_cb <= '0'; +bypass_cb <= '1'; +do_sum_cb_dly <= '0'; cb <= to_signed(0, 9); cb_dly1 <= to_signed(0, 9); elsif rising_edge(@{clk}) then @@ -271,7 +270,8 @@ end process multcr_process; sumcr_process : process (@{clk}, @{reset}) begin if @{reset} = '1' then -bypass_cr <= '0'; +bypass_cr <= '1'; +do_sum_cr_dly <= '0'; cr <= to_signed(0, 9); do_out_cr <= '0';