From: domas stephane <sdomas@912e006-01.iut-bm.univ-fcomte.fr>
Date: Fri, 23 Mar 2018 15:06:56 +0000 (+0100)
Subject: started top group gen, added project subdirs
X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/blast.git/commitdiff_plain/9bfa0c13066918f440ac2b5461fb3f8847f43fd6?ds=sidebyside

started top group gen, added project subdirs
---

diff --git a/top_group.vhd b/top_group.vhd
deleted file mode 100644
index 60ae10f..0000000
--- a/top_group.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
- -- VHDL generated automatically for top_group --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.numeric_std.all;
-entity top_group is 
-  port (
-    -- clk/rst
-    ext_clk : in std_logic;
-    ext_reset : in std_logic;
-    -- input data ports
-    
-    -- input control ports
-    
-    -- output data ports
-    
-    -- output control ports
-    
-    );
-
-end top_group;
-