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modif in VHDLConverter
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2017-12-08 stephane Domaschanges in output pattern comput
2017-10-15 stephane Domaschanged VHDL converter
2017-10-13 stephane Domaschanged name of the class that converts VHDL -> XML
2017-05-23 stephane Domascorrected some warnings
2017-05-22 domas stephanemodifying pattern methods to throw exceptions
2017-05-22 domas stephanefinished compat. computation
2017-05-22 stephane Domaspatter compat continued
2017-05-19 stephane Domasadded admittance computation
2017-05-18 stephane Domasmodified pattern to use only QMap
2017-05-14 stephane Domaspattern comput done
2017-05-12 stephane Domasstarted adding delta comput
2017-05-11 stephane Domasstarted to include patterns in implementation
2017-05-11 stephane Domasadded patterns and started OP computation
2017-05-10 stephane Domaschanged connection process
2017-05-10 stephane Domascorrect relative positionning of source/group
2017-05-09 stephane Domassource connection ok
2017-05-09 stephane Domasadded source items
2017-05-08 stephane Domasstart modifying read/write blocks and project to take...
2017-05-05 stephane Domasadded creation of control ifaces
2017-05-04 stephane Domasadding show/hide wb ifaces
2017-05-04 stephane Domasbegun integration of control ifaces
2017-05-03 Stéphane Domasadded impl xsd + patterns in impls
2017-05-03 stephane Domasloading project corrected
2017-04-27 stephane Domasinsert/move/remove block/groups/interface done. Next...
2017-04-26 Stéphane Domascorrecting bugs but still exsitings
2017-04-26 Stéphane Domas1st commit of all files