From e45bacc6bd342a1b19e42b62133ddabc99aa9edd Mon Sep 17 00:00:00 2001 From: sdomas Date: Thu, 22 Mar 2018 11:05:50 +0100 Subject: [PATCH 1/1] added sources managment --- BlockImplementation.h | 7 +- ExternalSource.cpp | 9 + ExternalSource.h | 33 ++++ MainWindow.cpp | 3 + Parameters.cpp | 93 ++++++++++- Parameters.h | 7 + blast.cpp | 5 +- blast.creator.user | 21 ++- blast.files | 2 + blastconfig.xml | 4 + blastconfig.xsd | 16 ++ implementation.xsd | 14 +- lib/implementations/boxfilter_3x3_impl.xml | 2 +- lib/implementations/impls.bmf | Bin 5790 -> 5790 bytes .../rgb3sx8_to_ycbcr_3DSP_impl.xml | 2 +- lib/sources/mult_accum.ngc | 3 + lib/sources/mult_accum.vhd | 103 ++++++++++++ lib/sources/ram_dp_1024x8.ngc | 3 + lib/sources/ram_dp_1024x8.vhd | 158 ++++++++++++++++++ lib/sources/ram_dp_2048x8.ngc | 3 + lib/sources/ram_dp_2048x8.vhd | 158 ++++++++++++++++++ lib/sources/tools_pkg.vhd | 11 ++ object-files.txt | 1 + 23 files changed, 636 insertions(+), 22 deletions(-) create mode 100644 ExternalSource.cpp create mode 100644 ExternalSource.h create mode 100644 lib/sources/mult_accum.ngc create mode 100644 lib/sources/mult_accum.vhd create mode 100644 lib/sources/ram_dp_1024x8.ngc create mode 100644 lib/sources/ram_dp_1024x8.vhd create mode 100644 lib/sources/ram_dp_2048x8.ngc create mode 100644 lib/sources/ram_dp_2048x8.vhd create mode 100644 lib/sources/tools_pkg.vhd diff --git a/BlockImplementation.h b/BlockImplementation.h index fb9c77c..aa08ed9 100644 --- a/BlockImplementation.h +++ b/BlockImplementation.h @@ -17,7 +17,6 @@ class ArithmeticEvaluator; #include "Exception.h" class Exception; - using namespace std; using namespace Qt; @@ -54,12 +53,14 @@ public: void loadPatterns(QDomElement &root) throw(Exception); bool checkPatterns(); - + inline void addSource(QString file) { sources.append(file); } private: QString xmlFile; QString referenceXml; QString referenceMd5; - QString nameEnt, line; + + QList sources; + QMap paramMap; ArithmeticEvaluator* evaluator; ReferenceBlock* reference; diff --git a/ExternalSource.cpp b/ExternalSource.cpp new file mode 100644 index 0000000..b0f8b32 --- /dev/null +++ b/ExternalSource.cpp @@ -0,0 +1,9 @@ +#include "ExternalSource.h" + + +ExternalSource::ExternalSource(const QString& _name, const QString& _file, int _type) { + + name = _name; + file = _file; + type = _type; +} diff --git a/ExternalSource.h b/ExternalSource.h new file mode 100644 index 0000000..5c244c4 --- /dev/null +++ b/ExternalSource.h @@ -0,0 +1,33 @@ +#ifndef __EXTERNALSOURCE_H__ +#define __EXTERNALSOURCE_H__ + +#include +#include + +#include + + +using namespace std; +using namespace Qt; + +class ExternalSource { + +public : + + enum SourceType { Code = 1, Package, Netlist, InitFile}; + + ExternalSource(const QString& _name, const QString& _file, int _type = Code); + + // getters + inline QString getName() { return name; } + inline QString getFile() { return file; } + inline int getType() { return type; } + +private: + QString name; + QString file; + int type; +}; + +#endif // __EXTERNALSOURCE_H__ + diff --git a/MainWindow.cpp b/MainWindow.cpp index 683ba3d..ad36484 100644 --- a/MainWindow.cpp +++ b/MainWindow.cpp @@ -24,6 +24,9 @@ MainWindow::MainWindow(QWidget *parent) : QMainWindow(parent) { try { params->loadBlastConfiguration("blastconfig.xml"); + // first load external sources + params->loadSources(); + if (!QFileInfo::exists(params->refLib)) { params->loadReferencesFromXml(); int ret = QMessageBox::question(this,tr("Building references library"),tr("The reference block library does not exists.\n References have been read directly from the xml descriptions of blocks.\n It can be saved into a library in order to start application faster. "), QMessageBox::Ok | QMessageBox::Cancel, QMessageBox::Ok); diff --git a/Parameters.cpp b/Parameters.cpp index 46437c3..c903f5d 100644 --- a/Parameters.cpp +++ b/Parameters.cpp @@ -574,10 +574,27 @@ void Parameters::loadBlastConfiguration(QString confFile) throw(Exception) { implPathes.append(path); cout << "impl path : " << qPrintable(path) << endl << endl; } + + QDomElement eltSource = eltImpl.nextSiblingElement("sources"); + nbPathesStr = eltSource.attribute("nb","none"); + nbPathes = nbPathesStr.toInt(&ok); + QDomNodeList listSourceDir = eltSource.elementsByTagName("source_lib"); + if ((!ok) || (nbPathes != listSourceDir.size())) throw(Exception(CONFIGFILE_CORRUPTED)); + + for(int i=0;i // for each child element, initialize the associated attributes of Parameters - QDomElement eltDefaults = eltImpl.nextSiblingElement("defaults"); + QDomElement eltDefaults = eltSource.nextSiblingElement("defaults"); QDomElement eltBlocks = eltDefaults.firstChildElement("blocks"); QString attributeStr = eltBlocks.attribute("width", "none"); @@ -807,6 +824,22 @@ void Parameters::loadImplementationsFromXml() throw(Exception) { QString refXml = implRoot.attribute("ref_name","none"); QString refMd5 = implRoot.attribute("ref_md5","none"); BlockImplementation* impl = new BlockImplementation(fileName,refXml,refMd5); + + QDomNodeList archNode = implRoot.elementsByTagName("architecture"); + + if (archNode.isEmpty()) { + cout << "impl has no architecture" << endl; + return; + } + QDomElement archElt = archNode.at(0).toElement(); + QString compList = archElt.attribute("comp_list","none"); + if (compList != "none") { + QStringList compos = compList.split(","); + foreach(QString s, compos) { + impl->addSource(s); + } + } + try { impl->loadPatterns(implRoot); } @@ -908,6 +941,64 @@ void Parameters::saveImplementationsToLib() throw(Exception) { libFile.close(); } + + +void Parameters::loadSources() throw(Exception) { + + for(int i=0;igetName() == name) return s; + } + return NULL; +} + void Parameters::addAvailableBlock(ReferenceBlock *block) { availableBlocks.append(block); foreach (int id,block->getCategories()) { diff --git a/Parameters.h b/Parameters.h index f03ca0a..0329130 100644 --- a/Parameters.h +++ b/Parameters.h @@ -24,6 +24,7 @@ class Graph; class GroupWidget; #include "BlockImplementation.h" +#include "ExternalSource.h" #include "Exception.h" class Exception; @@ -82,6 +83,7 @@ public : // others static QString normalizeName(const QString& name); + ExternalSource* searchSourceByName(const QString& name); /*************************************************** attributes that are general to the application @@ -89,8 +91,11 @@ public : BlockLibraryTree* categoryTree; QList refPathes; QList implPathes; + QList sourcePathes; QList availableBlocks; QList availableImplementations; + QList availableSources; + ReferenceBlock* delayRef; BlockImplementation* delayImpl; @@ -157,6 +162,8 @@ public : void loadImplementationsFromLib() throw(Exception); void saveImplementationsToLib() throw(Exception); + void loadSources() throw(Exception); + void addAvailableBlock(ReferenceBlock *block); void parametersValidation(); void connectionsValidation(); diff --git a/blast.cpp b/blast.cpp index b205eb2..35dd592 100644 --- a/blast.cpp +++ b/blast.cpp @@ -6,13 +6,12 @@ using namespace std; using namespace Qt; -int main(int argc, char *argv[]) -{ +int main(int argc, char *argv[]) { + QApplication a(argc, argv); MainWindow w; w.show(); return a.exec(); - } diff --git a/blast.creator.user b/blast.creator.user index 1aea169..8441c31 100644 --- a/blast.creator.user +++ b/blast.creator.user @@ -1,10 +1,10 @@ - + EnvironmentId - {3701e197-5b6c-48ea-9e98-a6cf6de18672} + {94112477-caab-4897-8f75-5f412f2c883a} ProjectExplorer.Project.ActiveTarget @@ -19,7 +19,7 @@ Cpp - qt2 + CppGlobal @@ -31,7 +31,7 @@ 2 UTF-8 false - 2 + 4 false 80 true @@ -43,12 +43,12 @@ true true 0 - 4 - false + 8 + true 1 true true - false + true false @@ -61,7 +61,7 @@ Desktop Desktop - {ed04208c-8774-456b-99b9-4a02094ca7a4} + {c934e180-ebc6-41ed-be82-502cc94f41f6} 0 0 0 @@ -128,7 +128,7 @@ false false - 0 + 1000 true @@ -169,9 +169,8 @@ - false %{buildDir} - Exécutable personnalisé + Custom Executable ProjectExplorer.CustomExecutableRunConfiguration 3768 diff --git a/blast.files b/blast.files index 2ef2768..01b85e5 100755 --- a/blast.files +++ b/blast.files @@ -1,3 +1,5 @@ +ExternalSource.h +ExternalSource.cpp CustomDialog.h CustomDialog.cpp NewProjectDialog.h diff --git a/blastconfig.xml b/blastconfig.xml index 0abb637..3544650 100644 --- a/blastconfig.xml +++ b/blastconfig.xml @@ -22,6 +22,10 @@ + + + + diff --git a/blastconfig.xsd b/blastconfig.xsd index ef4a2fa..6ad294a 100644 --- a/blastconfig.xsd +++ b/blastconfig.xsd @@ -112,6 +112,7 @@ + @@ -145,6 +146,12 @@ + + + + + + @@ -191,6 +198,15 @@ + + + + + + + + + diff --git a/implementation.xsd b/implementation.xsd index c838514..a42059f 100644 --- a/implementation.xsd +++ b/implementation.xsd @@ -15,6 +15,8 @@ + + @@ -100,8 +102,16 @@ - - + + + + + + + + + + diff --git a/lib/implementations/boxfilter_3x3_impl.xml b/lib/implementations/boxfilter_3x3_impl.xml index 50d2d0c..40f260f 100644 --- a/lib/implementations/boxfilter_3x3_impl.xml +++ b/lib/implementations/boxfilter_3x3_impl.xml @@ -13,7 +13,7 @@ - + component ram_dp_1024x8 port ( clka : in std_logic; diff --git a/lib/implementations/impls.bmf b/lib/implementations/impls.bmf index b69078a4664468635a51c6942ba6b7fc55fb2126..26cb30254bf85e13c2c49c733f624827b959ee0d 100644 GIT binary patch delta 75 zcmbQIJ5P5*GWXJ#f{I4dj6p)xaUw~_J dyMWT delta 73 zcmbQIJ5P5*GWX=|+zOM|a&t{i=Jwirox6l-@lRf#;CRg*nn!Hj#V)A?euF35J cN|RH8>|!zP&2I!eSto~z$xSvEQveA7000jf2LJ#7 diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml index e186114..e941579 100644 --- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml +++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml @@ -13,7 +13,7 @@ - + component mult_accum port ( @{clk} : in std_logic; diff --git a/lib/sources/mult_accum.ngc b/lib/sources/mult_accum.ngc new file mode 100644 index 0000000..a846bd9 --- /dev/null +++ b/lib/sources/mult_accum.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/lib/sources/mult_accum.vhd b/lib/sources/mult_accum.vhd new file mode 100644 index 0000000..59fc0f2 --- /dev/null +++ b/lib/sources/mult_accum.vhd @@ -0,0 +1,103 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2017 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file mult_accum.vhd when simulating +-- the core, mult_accum. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY mult_accum IS + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sclr : IN STD_LOGIC; + bypass : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + s : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END mult_accum; + +ARCHITECTURE mult_accum_a OF mult_accum IS +-- synthesis translate_off +COMPONENT wrapped_mult_accum + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sclr : IN STD_LOGIC; + bypass : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + s : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_mult_accum USE ENTITY XilinxCoreLib.xbip_multaccum_v2_0(behavioral) + GENERIC MAP ( + c_a_type => 0, + c_a_width => 18, + c_accum_mode => 0, + c_accum_width => 48, + c_b_type => 0, + c_b_width => 18, + c_bypass_low => 0, + c_ce_overrides_sclr => 0, + c_has_bypass => 1, + c_latency => 1, + c_out_width => 48, + c_round_type => 0, + c_use_dsp48 => 1, + c_verbosity => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_mult_accum + PORT MAP ( + clk => clk, + ce => ce, + sclr => sclr, + bypass => bypass, + a => a, + b => b, + s => s + ); +-- synthesis translate_on + +END mult_accum_a; diff --git a/lib/sources/ram_dp_1024x8.ngc b/lib/sources/ram_dp_1024x8.ngc new file mode 100644 index 0000000..4afd999 --- /dev/null +++ b/lib/sources/ram_dp_1024x8.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/lib/sources/ram_dp_1024x8.vhd b/lib/sources/ram_dp_1024x8.vhd new file mode 100644 index 0000000..d6459c5 --- /dev/null +++ b/lib/sources/ram_dp_1024x8.vhd @@ -0,0 +1,158 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2017 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file ram_dp_1024x8.vhd when simulating +-- the core, ram_dp_1024x8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY ram_dp_1024x8 IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ram_dp_1024x8; + +ARCHITECTURE ram_dp_1024x8_a OF ram_dp_1024x8 IS +-- synthesis translate_off +COMPONENT wrapped_ram_dp_1024x8 + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_ram_dp_1024x8 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 10, + c_addrb_width => 10, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 2, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 1024, + c_read_depth_b => 1024, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 1, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 1024, + c_write_depth_b => 1024, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram_dp_1024x8 + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb + ); +-- synthesis translate_on + +END ram_dp_1024x8_a; diff --git a/lib/sources/ram_dp_2048x8.ngc b/lib/sources/ram_dp_2048x8.ngc new file mode 100644 index 0000000..d9c70a4 --- /dev/null +++ b/lib/sources/ram_dp_2048x8.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/lib/sources/ram_dp_2048x8.vhd b/lib/sources/ram_dp_2048x8.vhd new file mode 100644 index 0000000..72c9294 --- /dev/null +++ b/lib/sources/ram_dp_2048x8.vhd @@ -0,0 +1,158 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2017 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file ram_dp_2048x8.vhd when simulating +-- the core, ram_dp_2048x8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY ram_dp_2048x8 IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ram_dp_2048x8; + +ARCHITECTURE ram_dp_2048x8_a OF ram_dp_2048x8 IS +-- synthesis translate_off +COMPONENT wrapped_ram_dp_2048x8 + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_ram_dp_2048x8 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 11, + c_addrb_width => 11, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 1, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 2, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 2048, + c_read_depth_b => 2048, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 1, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 2048, + c_write_depth_b => 2048, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram_dp_2048x8 + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb + ); +-- synthesis translate_on + +END ram_dp_2048x8_a; diff --git a/lib/sources/tools_pkg.vhd b/lib/sources/tools_pkg.vhd new file mode 100644 index 0000000..c32ddce --- /dev/null +++ b/lib/sources/tools_pkg.vhd @@ -0,0 +1,11 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package tools_pkg is + type vector_of_std_logic_vector18 is array (natural range <>) of std_logic_vector(17 downto 0); + type vector_of_std_logic_vector8 is array (natural range <>) of std_logic_vector(7 downto 0); + type vector_of_std_logic is array (natural range <>) of std_logic; + type vector_of_unsigned8 is array (natural range <>) of unsigned(7 downto 0); + type vector_of_std_logic_vector4 is array (natural range <>) of std_logic_vector(3 downto 0); +end tools_pkg; diff --git a/object-files.txt b/object-files.txt index 4df5ed7..3ced8a9 100644 --- a/object-files.txt +++ b/object-files.txt @@ -10,6 +10,7 @@ COMMON-OBJ = $(BUILDPATH)/AbstractBlock.o \ $(BUILDPATH)/AbstractInputModifier.o \ $(BUILDPATH)/DelayInputModifier.o \ $(BUILDPATH)/BlockImplementation.o \ + $(BUILDPATH)/ExternalSource.o \ $(BUILDPATH)/Graph.o \ $(BUILDPATH)/AbstractBoxItem.o \ $(BUILDPATH)/BoxItem.o \ -- 2.39.5