add chapter1, des trucs à régler

[book_gpu.git] / BookGPU / Chapters / chapter1 / ch1.tex

diff --git a/BookGPU/Chapters/chapter1/ch1.tex b/BookGPU/Chapters/chapter1/ch1.tex
index 42b018cf4686083d2f1c774f10f74cc4600a8a29..cf7a8b59e4b4119a7b729931f45a8ad3a4f5913e 100755 (executable)
--- a/BookGPU/Chapters/chapter1/ch1.tex
+++ b/BookGPU/Chapters/chapter1/ch1.tex
@@ -74,7 +74,7 @@ comparison with OpenCL, interested readers may refer to~\cite{ch1:CMR:12}.
 
 \section{Architecture of current GPUs}
 
 
 \section{Architecture of current GPUs}
 

-Architecture  \index{Architecture  of  a  GPU}  of current  GPUs  is  constantly
+Architecture  \index{architecture  of  a  GPU}  of current  GPUs  is  constantly

 evolving.    Nevertheless    some    trends    remains   true    through    this
 evolution.  Processing  units  composing a  GPU  are  far  more simpler  than  a
 traditional CPU but it is much easier to integrate many computing units inside a
 evolving.    Nevertheless    some    trends    remains   true    through    this
 evolution.  Processing  units  composing a  GPU  are  far  more simpler  than  a
 traditional CPU but it is much easier to integrate many computing units inside a


@@ -231,12 +231,12 @@ will explicit that.
 
 \section{Memory hierarchy}
 
 
 \section{Memory hierarchy}
 

-The memory hierarchy of  GPUs\index{Memory~hierarchy} is different from the CPUs
-one.  In practice,  there are registers\index{Memory~hierarchy!registers}, local
-memory\index{Memory~hierarchy!local~memory},                               shared
-memory\index{Memory~hierarchy!shared~memory},                               cache
-memory\index{Memory~hierarchy!cache~memory}              and              global
-memory\index{Memory~hierarchy!global~memory}.
+The memory hierarchy of  GPUs\index{memory~hierarchy} is different from the CPUs
+one.  In practice,  there are registers\index{memory~hierarchy!registers}, local
+memory\index{memory~hierarchy!local~memory},                               shared
+memory\index{memory~hierarchy!shared~memory},                               cache
+memory\index{memory~hierarchy!cache~memory}              and              global
+memory\index{memory~hierarchy!global~memory}.

 
 
 As  previously  mentioned each  thread  can access  its  own  registers.  It  is
 
 
 As  previously  mentioned each  thread  can access  its  own  registers.  It  is