X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/book_gpu.git/blobdiff_plain/8fd941eeeeccad914f5e2b833bc00c9d2401efd6..4df8b859fb5445134295e3e7a1df43d911d6d9dd:/BookGPU/Chapters/chapter3/ch3.aux?ds=sidebyside

diff --git a/BookGPU/Chapters/chapter3/ch3.aux b/BookGPU/Chapters/chapter3/ch3.aux
index 0f932fd..8a1e22e 100644
--- a/BookGPU/Chapters/chapter3/ch3.aux
+++ b/BookGPU/Chapters/chapter3/ch3.aux
@@ -84,7 +84,7 @@
 \@writefile{lof}{\contentsline {figure}{\numberline {4.9}{\ignorespaces Reducing register count in a 5$\times $5 register-only median kernel outputting 2 pixels simultaneously.}}{45}}
 \newlabel{fig:median5overlap}{{4.9}{45}}
 \@writefile{lof}{\contentsline {figure}{\numberline {4.10}{\ignorespaces First iteration of the $5\times 5$ selection process, with $k_{25}=14$, which shows how Instruction Level Parallelism is maximized by the use of an incomplete sorting network.}}{45}}
-\newlabel{fig:median5overlap}{{4.10}{45}}
+\newlabel{fig:bitonic}{{4.10}{45}}
 \newlabel{lst:medianForget2pix5}{{4.5}{46}}
 \@writefile{lol}{\contentsline {lstlisting}{\numberline {4.5}kernel 5$\times $5 median filter processing 2 output pixel values per thread by a combined forgetfull selection.}{46}}
 \@writefile{lot}{\contentsline {table}{\numberline {4.2}{\ignorespaces Performance of various 5$\times $5 median kernel implementations, applied on 4096$\times $4096 pixel image with C2070 GPU card.\relax }}{47}}
@@ -110,12 +110,12 @@
 \@writefile{lol}{\contentsline {lstlisting}{\numberline {4.6}generic pseudo median kernel.}{50}}
 \@writefile{toc}{\contentsline {section}{Bibliography}{51}}
 \@setckpt{Chapters/chapter3/ch3}{
-\setcounter{page}{52}
+\setcounter{page}{53}
 \setcounter{equation}{0}
 \setcounter{enumi}{3}
 \setcounter{enumii}{0}
 \setcounter{enumiii}{0}
-\setcounter{enumiv}{10}
+\setcounter{enumiv}{11}
 \setcounter{footnote}{0}
 \setcounter{mpfootnote}{0}
 \setcounter{part}{2}