--- /dev/null
+@article{ch19:matrix-collection,
+ author = {Duff, I. S. and Grimes, Roger G. and Lewis, John G.},
+ title = {Sparse matrix test problems},
+ journal = {ACM Trans. Math. Softw.},
+ issue_date = {March 1989},
+ volume = {15},
+ issue = {1},
+ month = {March},
+ year = {1989},
+ pages = {1--14},
+ acmid = {62043},
+ publisher = {ACM},
+ address = {New York, NY, USA},
+}
+
+@Conference{ch19:spmv-iccs,
+ author = {Dang, Hoang-Vu and Schmidt, Bertil},
+ title = {{The Sliced COO format for Sparse Matrix-Vector Multiplication on CUDA-enabled GPUs}},
+ year = {2012},
+ pages = {57-66},
+ booktitle = {Proc. ICCS, Procedia Vol. 9}
+}
+
+@article{ch19:spmv-ccpe,
+ author = {Bertil Schmidt and
+ Hans Aribowo and
+ Hoang-Vu Dang},
+ title = {{Iterative Sparse Matrix-Vector Multiplication for accelerating
+ the Block Wiedemann Algorithm over GF(2) on Multi-graphics
+ Processing Unit Systems}},
+ journal = {Concurrency and Computation: Practice and Experience},
+ volume = {25},
+ number = {4},
+ year = {2013},
+ pages = {586-603},
+}
+
+@misc{ch19:matview,
+ author = { Jim Kohl },
+ url = {http://www.csm.ornl.gov/~kohl/MatView/},
+ title = {MatView: Scalable Sparse Matrix Viewer},
+ year = {2008},
+}
+
+@inproceedings{ch19:nvidia-spmv,
+ author = {Bell, Nathan and Garland, Michael},
+ title = {Implementing sparse matrix-vector multiplication on throughput-oriented processors},
+ booktitle = {SC '09: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis},
+ year = {2009},
+ isbn = {978-1-60558-744-8},
+ pages = {1--11},
+ location = {Portland, Oregon},
+ doi = {http://doi.acm.org/10.1145/1654059.1654078},
+ publisher = {ACM},
+ address = {New York, NY, USA},
+}
+
+@article{ch19:bellpack,
+ author = {Choi, Jee W. and Singh, Amik and Vuduc, Richard W.},
+ title = {{Model-driven autotuning of sparse matrix-vector multiply on GPUs}},
+ journal = {SIGPLAN Not.},
+ volume = {45},
+ issue = {5},
+ month = {January},
+ year = {2010},
+ issn = {0362-1340},
+ pages = {115--126},
+ numpages = {12},
+ acmid = {1693471},
+ publisher = {ACM},
+ address = {New York, NY, USA},
+ keywords = {gpu, performance modeling, sparse matrix-vector multiplication},
+}
+
+@inproceedings{ch19:europar,
+ author = {Bertil Schmidt and
+ Hans Aribowo and
+ Hoang-Vu Dang},
+ title = { {Iterative Sparse Matrix-Vector Multiplication for Integer
+ Factorization on GPUs} },
+ booktitle = {Euro-Par (2)},
+ year = {2011},
+ pages = {413-424},
+ ee = {http://dx.doi.org/10.1007/978-3-642-23397-5_41},
+ crossref = {DBLP:conf/europar/2011-2},
+ bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+@proceedings{ch19:DBLP:conf/europar/2011-2,
+ editor = {Emmanuel Jeannot and
+ Raymond Namyst and
+ Jean Roman},
+ title = {Euro-Par 2011 Parallel Processing - 17th International Conference,
+ Euro-Par 2011, Bordeaux, France, August 29 - September 2,
+ 2011, Proceedings, Part II},
+ booktitle = {Euro-Par (2)},
+ publisher = {Springer},
+ series = {Lecture Notes in Computer Science},
+ volume = {6853},
+ year = {2011},
+ isbn = {978-3-642-23396-8},
+ ee = {http://dx.doi.org/10.1007/978-3-642-23397-5},
+ bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+@article{ch19:Thome:subqad,
+ author = {Thom\'{e}, Emmanuel},
+ title = { {Subquadratic Computation of Vector Generating Polynomials and Improvement of the Block Wiedemann Algorithm} },
+ journal = {J. Symb. Comput.},
+ volume = {33},
+ issue = {5},
+ month = {May},
+ year = {2002},
+ issn = {0747-7171},
+ pages = {757--775},
+ numpages = {19},
+ url = {http://portal.acm.org/citation.cfm?id=612306.612319},
+ doi = {10.1006/jsco.2002.0533},
+ acmid = {612319},
+ publisher = {Academic Press, Inc.},
+ address = {Duluth, MN, USA},
+}
+
+@ARTICLE{ch19:nfs,
+ author = {Peter L. Montgomery},
+ title = {A Survey of Modern Integer Factorization Algorithms},
+ journal = {CWI Quarterly},
+ year = {1994},
+ volume = {7},
+ pages = {337--366}
+}
+
+@article{ch19:wie,
+ author = {Wiedemann, D H},
+ title = {Solving sparse linear equations over finite fields},
+ journal = {IEEE Trans. Inf. Theor.},
+ volume = {32},
+ issue = {1},
+ month = {January},
+ year = {1986},
+ issn = {0018-9448},
+ pages = {54--62},
+ numpages = {9},
+ url = {http://dl.acm.org/citation.cfm?id=13738.13744},
+ doi = {10.1109/TIT.1986.1057137},
+ acmid = {13744},
+ publisher = {IEEE Press},
+ address = {Piscataway, NJ, USA},
+}
+
+@inproceedings{ch19:wie-guass,
+ author = {LaMacchia, Brian A. and Odlyzko, Andrew M.},
+ title = {Solving Large Sparse Linear Systems over Finite Fields},
+ booktitle = {Proceedings of the 10th Annual International Cryptology Conference on Advances in Cryptology},
+ series = {CRYPTO '90},
+ year = {1991},
+ isbn = {3-540-54508-5},
+ pages = {109--133},
+ numpages = {25},
+ url = {http://dl.acm.org/citation.cfm?id=646755.705355},
+ acmid = {705355},
+ publisher = {Springer-Verlag},
+ address = {London, UK, UK},
+}
+
+@book{ch19:book:mpi,
+ author = {Quinn, Michael},
+ edition = {1},
+ howpublished = {Hardcover},
+ isbn = {0072822562},
+ month = jun,
+ posted-at = {2010-04-02 13:14:26},
+ priority = {2},
+ publisher = {McGraw-Hill Science/Engineering/Math},
+ title = {{Parallel Programming in C with MPI and OpenMP}},
+ year = {2003}
+}
+
+@INPROCEEDINGS{ch19:mpi:col,
+ author = {Rajeev Thakur},
+ title = {Improving the performance of collective operations in MPICH},
+ booktitle = {Recent Advances in Parallel Virtual Machine and Message Passing Interface. Number 2840 in LNCS, Springer Verlag (2003) 257–267 10th European PVM/MPI User’s Group Meeting},
+ year = {2003},
+ pages = {257--267},
+ publisher = {Springer Verlag}
+}
+
+@INPROCEEDINGS{ch19:reduce_tree,
+ author = {Pitch Patarasuk and Xin Yuan},
+ title = {Bandwidth Efficient Allreduce Operation on Tree Topologies},
+ booktitle = {IEEE IPDPS Workshop on High-Level Parallel Programming Models and Supportive Environments},
+ year = {2007}
+}
+
+@InProceedings{ch19:aoki,
+ author = {Aoki, Kazumaro and Shimoyama, Takeshi and Ueda, Hiroki},
+ title = {{Experiments on the Linear Algebra Step in the Number Field Sieve}},
+ booktitle = {Proceedings of the Security 2nd international conference on Advances in information and computer security},
+ series = {IWSEC'07},
+ year = {2007},
+ isbn = {3-540-75650-7, 978-3-540-75650-7},
+ location = {Nara, Japan},
+ pages = {58--73},
+ numpages = {16},
+ _url = {http://portal.acm.org/citation.cfm?id=1778902.1778909},
+ acmid = {1778909},
+ publisher = {Springer-Verlag},
+ address = {Berlin, Heidelberg},
+ keywords = {block Lanczos, ethernet, integer factoring, number field sieve, parallel computation},
+}
+
+@InProceedings{ch19:kilobit,
+author = {Kazumaro Aoki and Jens Franke and Thorsten Kleinjung and Arjen K. Lenstra and Dag Arne Osvik},
+title = {{A Kilobit Special Number Field Sieve Factorization.}},
+booktitle = {ASIACRYPT},
+year = {2007}
+}
+
+@techreport{ch19:nvidia,
+ author = {Nathan Bell and Michael Garland},
+ title = {{Efficient Sparse Matrix-Vector Multiplication on {CUDA}}},
+ month = dec,
+ year = {2008},
+ institution = {NVIDIA Corporation},
+ type = {NVIDIA Technical Report},
+ number = {NVR-2008-004},
+}
+
+@TechReport{ch19:rsa170,
+author = {Dominik Bonenberger and Martin Krone},
+title = {{Factorization of RSA-170}},
+institution = {Ostfalia University of Applied Sciences},
+year = {2010},
+url = {http://public.rz.fh-wolfenbuettel.de/~kronema/pdf/rsa170.pdf},
+}
+
+@article{ch19:exactspmv,
+ author = {Brice Boyer and
+ Jean-Guillaume Dumas and
+ Pascal Giorgi},
+ title = {{Exact Sparse Matrix-Vector Multiplication on GPU's and Multicore
+ Architectures}},
+ journal = {CoRR},
+ volume = {abs/1004.3719},
+ year = {2010},
+ ee = {http://arxiv.org/abs/1004.3719},
+ bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+@article{ch19:bw,
+author = {Don Coppersmith},
+title = {{Solving Homogeneous Linear Equations Over GF(2) via Block Wiedemann Algorithm}},
+journal = {Mathematics of Computation},
+volume = {62},
+year = {1994},
+doi = {10.2307/2153413},
+masid = {1254705}
+}
+
+@InProceedings{ch19:hwang,
+ author = {Wontae Hwang and
+ Dongseung Kim},
+ title = {{Load Balanced Block Lanczos Algorithm over GF(2) for Factorization
+ of Large Keys}},
+ booktitle = {HiPC},
+ year = {2006},
+ pages = {375-386},
+ ee = {http://dx.doi.org/10.1007/11945918_38},
+ bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+@InProceedings{ch19:rsa768,
+author = {{Kleinjung, T., et al.}},
+title = {{Factorization of a 768-Bit RSA Modulus}},
+booktitle = {International Crytology Conference},
+year = {2010},
+pages = {333--350},
+doi = {10.1007/978-3-642-14623-7_18},
+masid = {13669015}
+}
+
+@article{ch19:hetero768,
+ author = {{Kleinjung, T., et al.}},
+ HAL_ID = {inria-00535765},
+ _URL = {http://hal.inria.fr/inria-00535765/en/},
+ title = { {A} {H}eterogeneous {C}omputing {E}nvironment to {S}olve the 768-bit {RSA} {C}hallenge},
+ language = {{A}nglais},
+ affiliation = {{L}aboratory for {C}ryptologic {A}lgorithms - {LACAL} - {\'E}cole {P}olytechnique {F}{\'e}d{\'e}rale de {L}ausanne - {NTT} {I}nformation {S}haring {P}latform {L}aboratories - {ISL} - {N}ippon {T}elegraph \& {T}elephone {C}orporation - {NTT} - {S}ilverbrook {R}esearch - silverbrook research - {D}epartment of {M}athematics - {U}niversity of {B}onn - {B}onn {U}niversit{\"a}t - {U}niversity of {B}onn - {CARAMEL} - {INRIA} {N}ancy - {G}rand {E}st / {LORIA} - {INRIA} - {CNRS} : {UMR}7503 - {U}niversit{\'e} {H}enri {P}oincar{\'e} - {N}ancy {I} - {U}niversit{\'e} {N}ancy {II} - {I}nstitut {N}ational {P}olytechnique de {L}orraine - {EPFL} / {D}omaine {IT} - {DIT} - {\'E}cole {P}olytechnique {F}{\'e}d{\'e}rale de {L}ausanne - {M}icrosoft {R}esearch - {M}icrosoft - {S}cientific {C}omputing and {C}ontrol {T}heory - {MAS}2 - {CWI} - {S}wiss {I}nstitute of {B}ioinformatics - {L}ausanne - {SIB} - {S}wiss {I}nstitute of {B}ioinformatics },
+ publisher = {{S}pringer-{V}erlag },
+ journal = {{C}luster {C}omputing },
+ audience = {internationale },
+ year = {2010},
+}
+
+@inproceedings{ch19:grid,
+ HAL_ID = {inria-00502899},
+ _URL = {http://hal.inria.fr/inria-00502899/en/},
+ title = { {Using a Grid Platform for Slving Large Sparse Linear Systems over {GF}(2)}},
+ author = {{K}leinjung, {T}horsten and {N}ussbaum, {L}ucas and {T}hom{\'e}, {E}mmanuel},
+ language = {{A}nglais},
+ affiliation = {{L}aboratory for {C}ryptologic {A}lgorithms - {LACAL} - {\'E}cole {P}olytechnique {F}{\'e}d{\'e}rale de {L}ausanne - {ALGORILLE} - {INRIA} {L}orraine - {LORIA} - {INRIA} - {CNRS} : {UMR}7503 - {U}niversit{\'e} {H}enri {P}oincar{\'e} - {N}ancy {I} - {U}niversit{\'e} {N}ancy {II} - {I}nstitut {N}ational {P}olytechnique de {L}orraine - {CARAMEL} - {INRIA} {N}ancy - {G}rand {E}st / {LORIA} - {INRIA} - {CNRS} : {UMR}7503 - {U}niversit{\'e} {H}enri {P}oincar{\'e} - {N}ancy {I} - {U}niversit{\'e} {N}ancy {II} - {I}nstitut {N}ational {P}olytechnique de {L}orraine },
+ booktitle = {11th {ACM}/{IEEE} {I}nternational {C}onference on {G}rid {C}omputing ({G}rid 2010) },
+ address = {{B}russels {B}elgique },
+ audience = {internationale },
+ month = {10},
+ year = {2010},
+}
+
+@inproceedings{ch19:sle,
+ author = {Alexander Monakov and
+ Anton Lokhmotov and
+ Arutyun Avetisyan},
+ title = {{Automatically Tuning Sparse Matrix-Vector Multiplication
+ for GPU Architectures}},
+ booktitle = {HiPEAC},
+ year = {2010},
+ pages = {111-125},
+ ee = {http://dx.doi.org/10.1007/978-3-642-11515-8_10},
+ bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+@inproceedings{ch19:bl,
+author = {Peter L. Montgomery},
+title = {{A Block Lanczos Algorithm for Finding Dependencies Over GF(2)}},
+booktitle = {Theory and Application of Cryptographic Techniques},
+year = {1995},
+pages = {106--120},
+masid = {674965}
+}
+
+@article{ch19:cuda,
+ author = {Nickolls, John and Buck, Ian and Garland, Michael and Skadron, Kevin},
+ title = {{Scalable Parallel Programming with CUDA}},
+ journal = {Queue},
+ issue_date = {March/April 2008},
+ volume = {6},
+ issue = {2},
+ month = {March},
+ year = {2008},
+ issn = {1542-7730},
+ pages = {40--53},
+ numpages = {14},
+ _url = {http://doi.acm.org/10.1145/1365490.1365500},
+ doi = {http://doi.acm.org/10.1145/1365490.1365500},
+ acmid = {1365500},
+ publisher = {ACM},
+ address = {New York, NY, USA},
+}
+
+@article{ch19:gpu,
+ author = {Nickolls, John and Dally, William J.},
+ title = {{The GPU Computing Era}},
+ journal = {IEEE Micro},
+ volume = {30},
+ issue = {2},
+ month = {March},
+ year = {2010},
+ issn = {0272-1732},
+ pages = {56--69},
+ numpages = {14},
+ acmid = {1804055},
+ publisher = {IEEE Computer Society Press},
+ address = {Los Alamitos, CA, USA},
+ keywords = {GPU computing, CUDA, scalable parallel computing, heterogeneous CPU\&\#x002B, GPU coprocessing, Tesla GPU architecture, Fermi GPU architecture, NVIDIA.},
+}
+
+@misc{ch19:cuda-guide,
+ author = {NVIDIA},
+ url = {http://developer.download.nvidia.com/compute/DevZone/docs/html/C/doc/CUDA_C_Programming_Guide.pdf},
+ title = {{CUDA C Programming Guide}},
+ year={2011},
+}
+
+@misc{ch19:p-reduction,
+ author = {Mark Harris},
+ url = {http://developer.download.nvidia.com/compute/cuda/1_1/Website/projects/reduction/doc/reduction.pdf},
+ title = {{Optimizing parallel reduction in CUDA}},
+ year={2007},
+}
+
+@misc{ch19:rsa190-factored,
+ url = {http://www.mersenneforum.org/showthread.php?t=14177},
+ title = {{RSA190 factored}},
+ year={2010}
+}
+
+@misc{ch19:cadonfs,
+ author = {{Gaudry, P., et al.}},
+ title = {{CADO-NFS}},
+ url = {http://cado-nfs.gforge.inria.fr/},
+ year = {2010}
+}
+
+@MISC{ch19:cusp,
+ author = "Nathan Bell and Michael Garland",
+ title = {{Cusp: Generic Parallel Algorithms for Sparse Matrix and Graph Computations}},
+ year = "2010",
+ url = "http://cusp-library.googlecode.com",
+ note = "Version 0.1.0"
+}
+
+@misc{ch19:msieve,
+ author = {Jason Papadopoulos},
+ title = {{Msieve}},
+ url = {http://sourceforge.net/projects/msieve/},
+ year = {2010}
+}
--- /dev/null
+\chapterauthor{Bertil Schmidt, Hoang-Vu Dang}{Johannes Gutenberg University of Mainz}
+
+\chapter{Solving large sparse linear systems for integer factorization on GPUs}
+\label{chapter19}
+
+\section{Introduction}
+\label{ch19:intro}
+
+The Number Field Sieve (NFS)\index{iterative methods!Number Field Sieve} is the current state-of-the-art integer factorization method. It requires the solution of a large sparse linear system over GF(2) (called the linear algebra step). The Block Wiedemann\index{Number Field Sieve!Block Wiedemann} (BW)\cite{ch19:bw} algorithm can be used to solve such a large sparse linear system efficiently using iterative sparse matrix vector multiplication (SpMV).
+
+Recent integer factorization efforts have been using CPU clusters to solve the large sparse linear system \cite{ch19:kilobit,ch19:rsa768}. The RSA-768 factorization \cite{ch19:rsa768}, for example, reported a runtime of 3 months for the linear algebra step on a cluster with 48 AMD dual hex-core CPUs. Previous work on parallelizing the linear algebra step focused on using CPU clusters and grids \cite{ch19:aoki,ch19:hwang,ch19:grid,ch19:hetero768}. In this chapter, we present a CUDA approach that can be used to accelerate the costly iterative SpMV operation for matrices derived from NFS.
+
+The memory access pattern in the SpMV operation generally consists of regular access patterns over the matrix and irregular access patterns over the vector. The irregular access pattern over the vector is a challenge that is pronounced more on the GPU than on the CPU, because of the smaller cache and the restrictive memory access pattern requirement to achieve maximum performance. However, a high-end GPU has an order-of-magnitude higher bandwidth than a high-end CPU; e.g. a GeForce GTX 580 has 192.4 GB/s memory bandwidth, while an Intel Core-i7 has a maximum of 25.6 GB/s memory bandwidth.
+
+SpMV on the GPU has been explored previously in several papers \cite{ch19:nvidia,ch19:exactspmv,ch19:bellpack,ch19:sle} for matrices derived from scientific computing applications. However, sparse matrices derived from NFS have generally different properties, i.e. they are larger, have a few dense rows and have many extremely sparse rows. The large size of the matrix causes the BL and BW algorithms to require a large number of SpMV iterations. This means that the time spent for matrix preprocessing and matrix data transfer to the GPU memory are negligible compared to the total runtime. Thus, approaches to SpMV on GPUs for NFS matrices may be different from previously published GPU SpMV approaches. We further present an extension of our SpMV method for binary-valued NFS matrices to single-precision floating-point matrices.
+
+\section{Block Wiedemann Algorithm}
+\label{ch19:block-wiedemann}
+
+The BW algorithm heuristically finds $n$ vectors in the kernel space \index{Number Field Sieve!kernel space}of a $d \times d$ binary matrix $B$, $n$ is one of two parameters $m, n$, called blocking factors\index{Number Field Sieve!blocking factors}. BW consists of the following steps:
+
+\begin{itemize}
+\item \textbf{Step 1 (BW1):} Compute the matrix sequence
+
+\begin{equation}
+A_i = x \cdot B^i \cdot y, \forall i=1,...,{\frac{d}{m}}+{ \frac{d}{n} }+O(1)
+\end{equation}
+
+ where $x,y$ are randomly chosen binary matrices of size $m \times d$ and $d \times n$ respectively.
+\item \textbf{Step 2 (BW2):} The Berlekamp-Massey\index{Number Field Sieve!Berlekamp-Massey} algorithm \cite{ch19:Thome:subqad} is used to compute a generating polynomial of the matrix sequence $A$ from BW1 in the form
+\begin{equation}
+F(X)= \sum_{i=1}^{{ \frac{d}{n} }+O(1)} {C_i \cdot X^i}
+\end{equation}
+where $C_i$ is a $n \times n$ binary matrix
+
+\item \textbf{Step 3 (BW3):} Compute the sequence of matrices $S$ of size $d \times n$ such that
+\begin{equation}
+S_i = B^i \cdot y \cdot C_i, \forall i=1,...,{\frac{d}{n}}+O(1)
+\end{equation}
+
+With high probability, $B \cdot \sum{S_i} = 0$ for which $\sum{S_i}$ is output as a solution.
+\end{itemize}
+
+We can treat $x$, $y$ and $S_i$ as vectors of block width $m$ or $n$. Assuming $B$ is a sparse matrix with $\gamma$ non-zeros per row on average and ignoring $m$ and $n$ as constant, the complexity of BW1 and BW3 is $O(\gamma d^2)$. Using the subquadratic algorithm by Thome \cite{ch19:Thome:subqad}, BW2 has a complexity of $O(d \log^2{d})$. Thus our approach to accelerate BW is based on accelerating BW1 and BW3 on a GPU while BW2 is still done on a CPU.
+
+\section{SpMV OVER GF(2) for NFS matrices using existing formats on GPUs}
+\label{ch19:existingspmv}
+ In this section, we review a few relevant previously published sparse matrix formats on GPUs and study their performance when applied to sparse matrices over GF(2) derived from integer factorization with NFS.
+
+ We consider the sparse binary matrix $B$ of size $d \times d$ and a dense vector $X$ of size $d \times n$ bit, where $n$ is called the \emph{blocking factor}. Mordern processors generally support 64-bit operations. Thus, typical blocking factors are of the form of $64 \cdot k, \; k \in \mathbb{N}$. Note that doubling the blocking factor roughly halves the number of SpMV iterations required but doubles the input vector size.
+
+ For all $0 \leq i \leq d-1$ let $c\_index[i]$ column index array of $B[i]$ which contains the indices of the non-zero entries of row $i$. Then, the following pseudocode shows a single SpMV iteration of $B$ with input vector $X$ and result vector $Y$.
+
+%% \begin{algorithm}
+%% \caption{SpMV-COLUMN-INDEX}
+%% \begin{algorithmic}
+%% \REQUIRE $c\_index[i]$: column array of rows $i$ of $B$;\\
+%% $X$: input vector
+%% \ENSURE $Y=B \cdot X$
+%% \FOR{$i=0$ to $d-1$}
+%% \STATE $Y[i]=0$
+%% \FORALL{$ind$ $\in$ $c\_index[i]$}
+%% \STATE $Y[i] = Y[i] \oplus X[ind]$
+%% \COMMENT{$\oplus:$ bitwise XOR operation}
+%% \ENDFOR
+%% \ENDFOR
+%% \end{algorithmic}
+%% \end{algorithm}
+
+
+\begin{algorithm}
+\caption{SpMV-COLUMN-INDEX}
+% \begin{algorithmic}
+ \KwIn{$c\_index[i]$: column array of rows $i$ of $B$}
+ \KwIn{ $X$: input vector}
+ \KwOut{ $Y=B \cdot X$}
+ \For{$i=0$ to $d-1$}{
+ $Y[i]=0$\;
+ \ForAll {$ind$ $\in$ $c\_index[i]$} {
+ $Y[i] = Y[i] \oplus X[ind]$\;
+ \CommentSty{$\oplus:$ bitwise XOR operation}
+}
+}
+% \end{algorithmic}
+\end{algorithm}
+
+
+ The costly operations in the SpMV pseudocode are the memory accesses for loading $ind$, $X[ind]$, $Y[i]$ and storing $Y[i]$. To speed up those operations on any architecture a common approach is to design a cache-friendly order of accessing the memory. The order is especially important for the vectors $X$ and $Y$, since their memory locations might be accessed multiple times. Accesses to $Y$ can be minimized by storing the intermediate results in fast memory and only write the accumulated result to $Y$.
+
+ CUDA implementations of SpMV generally store both matrix and vectors in \emph{global memory}. Memory accesses to $B$ and $Y$ can usually be coalesced. Memory accesses to $X$ are random and non-coalesced thus having higher latency, but \emph{texture memory} can be used to take advantage of the \emph{texture cache}. Intermediate results could utilize \emph{shared memory} which has low latency however is very limited in size and only shared between threads of the same block. Shared memory is further divided into \emph{banks}. When threads in a warp access the shared memory, \emph{bank conflicts} should be avoided otherwise the access will be serialized.
+
+ We now briefly review the CUDA implementation of a number of SpMV matrix formats published in previous papers \cite{ch19:nvidia,ch19:sle}. We also describe the data structure in which the matrix in Figure \ref{fig:ex_matrix} is stored using the format as an example. Please note that when storing a binary matrix, the $value$ array can be removed.
+
+\begin{figure}[t]
+ \centering
+ \includegraphics[width=4cm]{Chapters/chapter19/fig/ex_matrix.pdf}
+ \caption{An example square matrix of size $6 \times 6$ (zero values are not shown)}
+ \label{fig:ex_matrix}
+\end{figure}
+
+ \subsubsection*{Coordinate list (COO)\index{Compressed storage format!COO}}
+For each non-zero, both its column and row indices are explicitly stored. The Cusp implementation \cite{ch19:cusp} stores elements in sorted order of row indices ensuring that entries with the same row index are stored contiguously.
+
+ \begin{lstlisting}
+ coo.row_index = {0, 1, 1, 2, 2, 3, 3, 3, 4, 5, 5}
+ coo.col_index = {2, 1, 4, 1, 3, 0, 2, 4, 2, 0, 5}
+ coo.value = {3, 1, 5, 2, 4, 6, 8, 10, 9, 7, 11}
+ \end{lstlisting}
+
+ \subsubsection*{Compressed Sparse Row (CSR)\index{Compressed storage format!CSR}} Non-zeros are sorted by the row index, and only their column indices are explicitly stored in a column array. Additionally, the vector $row\_start$ stores indices of the first non-zero element of each row in the column array.
+
+ \begin{lstlisting}
+ csr.row_start = {0, 1, 3, 5, 8, 9, 12}
+ csr.col_index = {2, 1, 4, 1, 3, 0, 2, 4, 2, 0, 5}
+ csr.value = {3, 1, 5, 2, 4, 6, 8, 10, 9, 7, 11}
+ \end{lstlisting}
+
+ \subsubsection*{Ellpack (ELL)\index{Compressed storage format!ELL}} Let $K$ be the maximum number of non-zero elements in any row of the matrix. Then, for each row, ELL stores exactly $K$ elements (extra padding is required for rows that contain less than $K$ non-zero elements). Only column indices are required to store in an array, the row index can be implied since exactly $K$ elements are stored per row. The Cusp implementation store the column indices in a transposed manner so that consecutive threads can access consecutive memory addresses.
+
+ \begin{lstlisting}
+ ell.col_index = {
+ 2, 1, 1, 0, 2, 0,
+ *, 4, 3, 2, *, 5,
+ *, *, *, 4, *, *}
+ ell.value = {
+ 3, 1, 2, 6, 9, 7,
+ *, 5, 4, 8, *, 11,
+ *, *, *, 10, *, *}
+ \end{lstlisting}
+
+ \subsubsection*{Hybrid (HYB)\index{Compressed storage format!HYB}} The HYB format heuristically computes an value $K$ and store $K$ non-zeros per rows in the ELL format. When a row has more than $K$ non-zeros, the trailing non-zeros are stored in COO. This design decreases the storage overhead due to ELL padding elements and thus improve the overall performance.
+ \begin{lstlisting}
+ hyb.nnz_per_row = 2
+ hyb.ell.col_index = {2, 1, 1, 0, 2, 0, *, 4, 3, 2, *, 5}
+ hyb.ell.value = {3, 1, 2, 6, 9, 7, *, 5, 4, 8, *, 11}
+ hyb.coo.row_index = {3}
+ hyb.coo.col_index = {4}
+ hyb.coo.value = {10}
+ \end{lstlisting}
+
+ \subsubsection*{Sliced Ellpack (SLE)\index{Compressed storage format!SLE}} This format partitions the matrix into horizontal slices of $S$ adjacent rows \cite{ch19:sle}. Each slice is stored in ELLPACK format. The maximum number of non-zeros may be different for each slice. An additional array $slice\_start$ is used to index the first element in each slice. The matrix rows are usually sorted by the number of non-zeros per row in order to move rows with similar number of non-zeros together.
+ \begin{lstlisting}
+ sle.slice_size = 2
+ sle.col_index = {
+ 2, 1, *, 4,
+ 1, 0, 3, 2, *, 4,
+ 2, 0, *, 5}
+ sle.value = {
+ 3, 1, *, 5,
+ 2, 6, 4, 8, *, 10
+ 9, 7, *, 11}
+ sle.slice_start = {0, 4, 10, 14}
+ \end{lstlisting}
+
+ \begin{table}
+ \caption{Properties of some NFS matrices}
+ \centering
+ \begin{tabular}
+ {| l || c | c | c | c | c | c |}
+ \hline
+ & RSA-170 & RSA-190 & KILOBIT & RSA-768 \\
+ \hline
+ Max dimension & 10.4M & 26.1M & 66.7M & 192M \\
+ Non-zeros & 994.7M & 2,451M & 9,538M & 27,797M\\
+ Max row weight & 5.5M & 14M & 28.2M & 82.6M\\
+ Min row weight & 3 & 3 & 2 & 2\\
+ Avg row weight & 95.08 & 93.6 & 143 & 144\\
+ \hline
+ \end{tabular}
+
+ \label{table:rsa_matrix}
+ \end{table}
+
+The existing formats do not achieve good performance due to the special structure of NFS matrices. Row weights of an NFS matrix have a very wide range (see Table \ref{table:rsa_matrix}). Hence using one warp or one thread per row (as in CSR or ELLPACK) results in an unbalanced workload. Moreover, the NFS matrices are highly unstructured, which does not facilitate cache-friendly vector access patterns using existing formats. These reasons have motivated our design of a new format.
+
+\section{A hybrid format for SpMV on GPUs}
+\label{Implementation}
+
+As a preprocessing step, we reorder the rows of the matrix by their \emph{row weight}, in non-increasing order. The row weight of row $j$ of $B$ is defined as the total number of non-zero elements in row $j$. We then partition the sorted matrix rows into at most four consecutive parts. Each part uses a different format. The different formats are optimized for the sparseness properties of each partition as shown in Figure \ref{fig:partitioning}. For the densest part, we use a dense format. When the matrix gets less dense, we switch to another format which we call \index{Compressed storage format!Sliced COO} Sliced COO (SCOO). SCOO has three variants, small, medium, and large. Our formats are now described in more detail.
+
+\begin{figure}[t]
+ \centering
+ \includegraphics[scale=1.3]{Chapters/chapter19/fig/partitioning.pdf}
+ \caption{Partitioning of a row-sorted NFS matrix into four formats}
+ \label{fig:partitioning}
+\end{figure}
+
+ \subsection{Dense Format}
+ The dense format is used for the dense part of the matrix. This format uses 1 bit per matrix entry. Within a column, 32 matrix entries are stored as a 32 bit integer. Thus, 32 rows are stored as $N$ consecutive integers.
+
+ Each CUDA thread works on a column. Each thread fetches one element from the input vector in coalesced fashion. Then, each thread checks the 32 matrix entries one by one. When the matrix entry is a non-zero, the thread performs a XOR operation between the element from the input vector and the partial result for the row. This means each thread only accesses the input vector once to do work on up to 32 non-zeros. The partial result from each thread needs to be stored and combined to get the final result for the 32 rows. These operations are performed in CUDA shared memory.
+
+ The 32 threads in a warp share 32 shared memory entries to store the partial results from the 32 rows. Since all threads in a warp execute a common instruction at a time, access to these 32 entries can be made exclusive. The result from each warp in a thread block is combined using p-reduction on shared memory. The result from each thread block is combined using an atomic XOR operation on global memory.
+
+ When the blocking factor is larger than 64, access to the shared memory needs to be reorganized to avoid bank conflicts. Each thread can read/write up to 64 bit data at a time to the shared memory. If a thread is accessing 128 bit data for example, two read/write operations need to be performed. Thus, there will be bank conflicts if we store 128 bit data on contiguous addresses. We can avoid bank conflicts by having the threads in a warp first access consecutive 64 bit elements representing the first halves of the 128 bit elements. Then, the threads again access consecutive 64 bit elements representing the second halves of the 128 bit elements. The same modification can be applied to other formats as well.
+
+ \subsection{Sliced COO}
+ The SCOO format is adapted from the CADO-NFS software for CPUs \cite{ch19:cadonfs}. The aim is to reduce irregular accesses to the input vector and increase the texture cache hit rate. SCOO stores the column index and the row index of each non-zero. A number of consecutive rows form a slice. Non-zeros within a slice are sorted by their column index. We give an example of SCOO in Figure \ref{fig:scoo-1}, threads working on a slice can access contiguous elements from the input vector. In the figure, S1, S2 are two slices. Entries in the input vector denote the corresponding non-zero elements that the input vector element is multiplied with.
+
+ For each non-zero, two bytes are used to store the column index. However, two bytes are not enough for large RSA matrices. Thus, we further divide a slice into groups. Group $i$ contains non-zeros with column index between $i \times 2^{16}$ and $(i+1) \times 2^{16} - 1$. An additional array stores the starting position of each group in the slice.
+
+ \begin{figure}[t]
+ \centering
+ \includegraphics[height=5cm]{Chapters/chapter19/fig/scoo.pdf}
+ \caption{Example of the memory access pattern for a $6 \times 6$ matrix stored in Sliced COO format (Slice Size = 3 rows).}
+ \label{fig:scoo-1}
+ \end{figure}
+
+
+\lstinputlisting[label=ch19:lst:spmv,caption=SpMV with SCOO format]{Chapters/chapter19/code.cu}
+
+ One thread block works on a slice, one group at a time. Neighboring threads work on neighboring non-zeros in the group in parallel. Each thread works on more than one row of the matrix. Thus, each thread needs some storage to store the partial result and combine them with the result from the other threads to generate the final output. Each entry costs equally as the element of the vector i.e. the blocking factor in byte. Shared memory is used as intermediate storage as they have low latency however it is limited to 48 KB per SM in Fermi. The global memory is only accessed once at the end to write the final output. The CUDA kernel for SpMV with Sliced COO format is shown in Listing \ref{ch19:lst:spmv}.
+
+ Since neighboring non-zeros may or may not come from the same row (recall that we sorted them by column index), many threads may access the same entry in the shared memory if it is used to store result of the same rows. Thus, shared memory entries are either assigned exclusively to a single thread or shared by using atomic XOR operations. Based on the way we allocate the shared memory, we further divide the Sliced COO format into three different subformats: small, medium, and large.
+
+ \begin{table}
+ \caption{Sliced COO subformat comparison (\# rows per slices is based on $n=64$) }
+ \centering
+ \begin{tabular}
+ { | c || c | c | c |}
+ \hline
+ Sliced COO subformats & Small & Medium & Large \\
+ \hline
+ Memory Sharing & No sharing & Among Warp & Among Block\\
+ Access method & Direct & Atomic XOR & Atomic XOR\\
+ Bank conflict & No & No & Yes\\
+ \# Rows per Slice & 12 & 192 & 6144 \\
+ \hline
+ \end{tabular}
+ \label{table:scoo}
+ \end{table}
+
+ \subsubsection*{Small Sliced (SS) COO}
+ In this subformat, each thread has one exclusive entry in shared memory to store the partial result for each row. The assignment of the shared memory is organized such that each thread in a warp accesses only one bank and there is no bank accessed by more than one thread. Thus, there is no bank conflict. A p-reduction operation on shared memory is required to combine partial results from each thread.
+
+ The maximum number of rows per slice is calculated as \emph{size of shared memory per SM in bits / (number of threads per block * blocking factor)}. We use 512 threads per block for 64 bit blocking factor which gives 12 rows, and 256 threads per block for 128 and 256 bit blocking factor, which gives 12 and 6 rows, respectively. Hence, one byte per row index is sufficient for this subformat.
+
+ \subsubsection*{Medium Sliced (MS) COO}
+ In this subformat, each thread in a warp gets an entry in the shared memory to store the partial result for each row. However, this entry is shared with the threads in other warps. Access to the shared memory uses an atomic XOR operation. Each thread in a warp accesses only one bank, avoiding bank conflicts. A p-reduction operation on shared memory is required to combine the 32 partial results.
+
+ The maximum number of rows per slice is calculated as \emph{size of shared memory per SM in bits / (32 * blocking factor)} where 32 is the number of threads in a warp. This translates to 192, 96, and 48 rows per slice for blocking factor of 64, 128, and 256 bit, respectively. Hence, one byte per row index is sufficient for this format.
+
+ \subsubsection*{Large Sliced (LS) COO}
+ In this subformat, the result for each row gets one entry in shared memory, which is shared among all threads in the thread block. Access to shared memory uses an atomic XOR operation. Thus, there will be bank conflicts. However, this drawback can be compensated by a higher texture cache hit rate. There is no p-reduction on shared memory required.
+
+ The maximum number of rows per slice is calculated as \emph{size of shared memory per SM in bits / blocking factor}. This translates to 6144, 3072, and 1536 rows per slice for blocking factor of 64, 128, and 256 bit, respectively. We use two bytes for the row index.
+ \linebreak
+ \linebreak
+ \noindent Table \ref{table:scoo} summarizes the differences between the three subformats.
+ \begin{itemize}
+ \item[a)] Each thread in a block is allocated one memory entry for the result of a row and works on consecutive 12 rows. A p-reduction to Thread\#1 is needed to get the final result of one row.
+ \item[b)] Each warp in a block is allocated one memory entry per row and works on 192 consecutive rows, threads in each warp use atomic XOR to update the value in a given entry. A p-reduction for each row to memory in Warp\#1 is needed to obtain the final result of that row.
+ \item[c)] A thread block works on 6144 consecutive rows and share the memory entry of each row. Any update to the memory has to use atomic XOR.
+ \end{itemize}
+
+ \subsection{Determining the cut-off point of each format}
+ \label{ch19:mat-partition-1}
+ To determine which format to use, we compare the performance of two consecutive formats in terms of giga non-zeros (\emph{gnnz}) per second for a given matrix, starting with the dense format and the SS-COO format. The two formats start from the same row (starting from the first row) and work on the minimum number of rows possible. For the dense format, the minimum number of rows is 32. For the SS-COO format (and its variants), the minimum number of rows is \emph{the number of rows in a slice} times \emph{the number of multiprocessors in the GPU}, since one thread block works on one slice and one thread block is assigned to one multiprocessor.
+
+ The next comparison depends on the result of the current comparison. If the dense format performs better, we decide to use it for rows 1 to 32, and we continue comparing the dense format and the SS-COO format starting from row 33. However, if the SS-COO format performs better, we compare its performance with the next format, MS-COO, starting from the same row, and so on. The idea is to stop considering the denser format once the sparser format outperforms it. Once we get to the comparison between MS-COO and LS-COO, and LS-COO performs better, we don't need to do any further comparisons. LS-COO should be used for the rest of the matrix.
+
+ For Sliced COO format, it is essential to note that when one slice is assigned to each multiprocessor, the load for one multiprocessor may be much higher than that of the other multiprocessors. This is because the matrix rows have been reordered by their weight in a non-increasing order, so the first slice contains more non-zero entries than the rest. Thus, we need to further reorder the rows such that each multiprocessor gets the same level of load.
+
+ The cut-off point determination is performed once per matrix and as a preprocessing step. Its runtime is equivalent to less than five iterations of SpMV.
+
+
+\section{SCOO for Single-Precision Floating-Point Matrices}
+The design of SCOO depends on performing atomic operations to combine the partia results. Atomic operations for double-precision are not available on current CUDA-enabled devices. Thus, we only present the SCOO extension for single-precision floating-point matrices.
+
+To extend SCOO for genereal matrices in real numbers, we first adapt to the variety of sparsity in real number matrices. Unlike NFS matrices, the sparsity is not predictable. Hence instead of using three subformats (SS-COO, MS-COO, LS-COO) with a fixed slice size (12, 192, 6144), we make the slice size a variable. Let $h$ denote the slice size, $S$ denote the size in byte of shared memory per thread block ($S=49152$ for Fermi) and $b$ denote the size of each matrix value in byte ($b=4$ for single-precision floating point). $h$ must be a positive integer value of the form of $h = \frac{S}{2^{i} b}$, $\forall{0 \leq i \leq T}$ where $T=\log_2{\textit{(maximum number of thread per block)}}$.
+
+For example in Fermi GPUs, single-precision floating point, $h \in \{12288, 6144, 3072, 1536, 768, 384, 192, 96, 48, 24, 12\}$ for $S=49152, b=4, T=10$. The algorithm in Section \ref{ch19:mat-partition-1} can be used to determine the cut-off point for each sub-formats. Figure \ref{fig:final-scoo} illustrates the final matrix in SCOO format assuming the number of multiprocessors in the GPU is $5$ and the row index is ranging from $0..d-1$. $H_i$ and $r_i$ is the slice size and starting row index of the sub-matrix $i$.
+
+\begin{figure}[t]
+ \centering
+ \includegraphics[width=8cm]{Chapters/chapter19/fig/final-scoo-book.pdf}
+ \caption{Partitioning of a row-sorted floating-point matrix into SCOO format.}
+ \label{fig:final-scoo}
+\end{figure}
+
+More details of the SCOO format for floating-point matrices can be found in \cite{ch19:spmv-iccs}
+
+\section{Performance Evaluation}
+\label{ch19:result}
+
+\subsection{Experimental Setup}
+\begin{table}
+\caption{Overview of hardware used in the experiments}
+\begin{center}
+\begin{tabular}{|l|l|l|l|}
+\hline
+Hardware & C2075 & GTX-580 & Core-i7 2700K\\
+\hline
+\# Cores &448& 512 & 4\\
+\hline
+Clock speed (Ghz)&1.15& 1.57 &3.5\\
+\hline
+Memory type & GDDR5 & GDDR5 & DDR3-1600 \\
+\hline
+Memory size (GB)&6 & 3 &16\\
+\hline
+Max Memory bandwidth (GB/s)& 144 & 192 & 21 \\
+\hline
+\end{tabular}
+\end{center}
+\label{table:hardware}
+\end{table}
+
+Table \ref{table:hardware} specifies the GPUs and the CPU workstation used for performance evaluation. The performance is measured in terms of $ggnz$ and $Gflop/s$ for binary and floating-point matrices. Measured GPU performance does neither include PCIe data transfers nor matrix preprocessing. These are realistic assumptions since SpMV applications usually consist of a large number of iterations where the sparse matrix is iteratively multiplied by the input/output vectors.
+
+Our source code is compiled and executed using CUDA toolkit and driver version $4.2$ under Linux Ubuntu 12.04.
+
+\subsection{Experimental results of SpMV on NFS matrix}
+We have evaluated our implementation on an NVIDIA Tesla C2075 (ECC disabled) with 6 GB RAM. We have compared the GPU performance with the open-source CADO-NFS \cite{ch19:cadonfs} program running on Intel Core i7-920 CPU with 12 GB DDR3-1066 memory. The RSA-170 matrix (see Table \ref{table:rsa_matrix}) is used for performance evaluation.
+
+The speedups compared to the multi-threaded CADO-NFS bucket implementation on an Intel Core i7-920 are given in brackets. The GPU memory required to store the sparse matrix and the corresponding bytes per non-zero (nnz) are also reported. CADO-NFS contains several CPU optimized SpMV implementations using multi-threading and SSE instructions. In this experiment, we compare the performance of our implementation to the CPU cache-optimized bucket format of CADO-NFS using 8 threads.
+
+\begin{table}[t]
+ \caption{Performance of SpMV on RSA-170 matrix}
+ \label{table:rsa170}
+ \centering
+ \begin{tabular}
+ { | c || c | c | c | c |}
+ \hline
+ Blocking & C2075 & 2 x C2075 & Core i7-920 & GPU memory \\
+ factor & (speedup) & (speedup) & CADO-NFS & (bytes/nnz) \\
+ \hline
+ 64 & 4.28 (4.9) & 8.38 (9.5) & 0.88 & 2748 MB (2.90)\\
+ 128 & 2.78 (5.6) & 5.37 (10.7) & 0.5 & 2967 MB (3.13)\\
+ 256 & 1.88 (7.0) & 3.68 (13.6) & 0.27 & 3000 MB (3.16)\\
+
+ \hline
+ \end{tabular}
+\end{table}
+
+ Table \ref{table:rsa170} shows the result. The dual-GPU implementation achieves speedups between 1.93 and 1.96 compared to the single-GPU performance.
+
+ Table \ref{table:individual} show the individual performance of each sub-format (in \emph{gnnz/s}), the percentage of non-zeros are included in bracket. The result show that the performance decreases when the matrix gets sparser. The MS-COO and LS-COO performance degrade when the blocking factor is increased from 64 to 128 and 256 bit. This is caused by the increased number of bank conflicts and serialization of atomic XOR operations on larger blocking factors. Thus, the SS-COO format gets a higher percentage of non-zeros with 128 and 256 bit blocking factor.
+
+ More detail results of our full Block Wiedemann CUDA implementation as well as a multi-GPU implementation can be found in \cite{ch19:spmv-ccpe}
+
+\begin{table}[h]
+ \caption{Performance for each of the four sub-format partitions of the RSA-170 matrix on a C2075.}
+ \label{table:individual}
+ \centering
+ \begin{tabular}
+ { | c || c | c | c | c | c |}
+ \hline
+ Blocking factor & Dense & SS-COO & MS-COO & LS-COO \\
+ \hline
+ 64 & 13.66 (24\%) & 9.66 (11\%) & 8.13 (13\%) & 2.77 (52\%) \\
+ 128 & 9.66 (15\%) & 7.53 (24\%) & 3.23 (6\%) & 1.86 (55\%) \\
+ 256 & 7.00 (15\%) & 4.21 (21\%) & 2.34 (6\%) & 1.33 (58 \%) \\
+ \hline
+ \end{tabular}
+\end{table}
+
+\subsection{Experimental results of SpMV on floating-point matrices}
+\label{ch19:result-2}
+\npthousandsep{,}
+
+\begin{table}
+\caption{Overview of sparse matrices used for performance evaluation}
+\begin{center}
+\begin{tabular}{|l|n{8}{0}|n{9}{0}|n{3}{2}|l|}
+\hline
+{Name} & row & column & nz/row & Description \\
+\hline
+GL7d19 &1911130&1955309&19.53& combinatorial problem \\
+\hline
+relat9 &12360060&549336&3.15& combinatorial problem \\
+\hline
+wikipedia-20070206 &3566907&3566907&12.62& directed graph \\
+\hline
+wb-edu &9845725&9845725&5.81& directed graph\\
+\hline
+road\_usa &23947347&23947347&2.41& undirected graph \\
+\hline
+hugebubbles-00010 &19458087&19458087&3.00& undirected graph \\
+\hline
+circuit5M &5558326&5558326&10.71&circuit simulation\\
+\hline
+nlpkkt120 &3542400&3542400&26.85&optimization problem\\
+\hline
+cage15 &5154859&5154859&19.24&directed weighted\\
+\hline
+kron\_g500-logn21 &2097152&2097152&86.82&undirected multigraph\\
+\hline
+indochina-2004&7414866&7414866&26.18& directed graph \\
+\hline
+nlpkkt160 &8345600&8345600&27.01&optimization problem\\
+\hline
+rgg\_n\_2\_24\_s0 &16777216&16777216&15.80&undirected random\\
+\hline
+uk-2002 &18520486&18520486&16.10&directed graph\\
+\hline
+\end{tabular}
+\end{center}
+\label{table:matrices}
+\end{table}
+
+\begin{figure}
+\label{fig:mat-visual}
+\centering
+ \subfigure[nlpkkt120] {
+ \includegraphics[width=100pt]{Chapters/chapter19/fig/matrix-str.pdf}
+ \label{fig:mat-str}
+ }
+ \subfigure[Relat9 - first 10000 rows] {
+ \includegraphics[width=100pt]{Chapters/chapter19/fig/matrix-mid.pdf}
+ \label{fig:mat-mid}
+ }
+ \subfigure[GL7d19 - first 500 rows and columns] {
+ \includegraphics[width=100pt]{Chapters/chapter19/fig/matrix-uns.pdf}
+ \label{fig:mat-unstr}
+ }
+
+ \caption{Visualization of \emph{nlpkkt120}, \emph{Relat9}, and \emph{GL7d19} matrix.}
+\end{figure}
+
+\begin{figure}
+\centering
+\includegraphics[height=5cm]{Chapters/chapter19/fig/scoo-a.pdf}
+\caption{Performance comparison of SCOO and other GPU formats for each test matrix on a Fermi Tesla C2075 (ECC disabled).}
+\label{fig:scoo-vs-gpu}
+\end{figure}
+
+\subsubsection{Performance comparison to existing GPU formats}
+We compare the performance of our SCOO format to available SpMV implementations on both GPU and CPU. The set of selected test matrices are collected from the University of Florida Sparse Matrix Collection \cite{ch19:matrix-collection}. We have chosen the biggest matrices from different areas that with their corresponding input and output vector can still fit into the 6GB global memory of a C2075 GPU. Table \ref{table:matrices} gives an overview of those matrices.
+
+We compare the SCOO format to the CSR, COO and HYB format of Cusp 0.3.0. Other Cusp formats are not able to run on the large tested matrices that we selected. The results are shown in Figure \ref{fig:scoo-vs-gpu}. The performance are in terms of Gflop/s which is based on the assumption of two flops per non-zero entry of the matrix \cite{ch19:nvidia-spmv, ch19:bellpack}.
+
+The SCOO format achieves a stable performance for different matrices in single-precision mode. In most cases a performance of over 10 Gflop/s can be sustained. For some highly unstructured matrices such as \emph{GL7d19}, \emph{wikipedia-20070206}, \emph{rgg\_n\_2\_24\_s0} and \emph{kron\_g500-logn21} SCOO achieves high speedups ranging from 3 to 6 compared to the best performaning Cusp format.
+
+For most matrices, HYB produces the best performance among the tested Cusp formats. HYB is able to outperform SCOO only for two matrices: \emph{nlpkkt120} and \emph{nlpkkt160}. Both matrices have a similar structure i.e. they consist of consecutive rows that have a very similar number of non-zero coefficients which is suitable to be stored in the ELL section of the HYB format. Moreover the non-zeros are close to each other facilitating coaleasing and cache-friendly access patterns by nature. SCOO is able to outperform COO and CSR for all tested matrices.
+
+In matrix $Relat9$ we observe some patterns but the matrix is still generally unstructured, thus SCOO is able to achieve about 2 times speed up compared to HYB which is the best among tested Cusp formats in this case. The average speedup of SCOO for the tested matrices is 3.0 compared to CSR, 5.02 compared to COO, 2.15 compared to HYB.
+
+We show the visualization of sparse matrices \emph{nlpkkt120}, \emph{Relat9}, \emph{GL7d19} in Figure \ref{fig:mat-str}, \ref{fig:mat-mid}, {fig:mat-unstr} using MatView \cite{ch19:matview}. The white color represents zero entries, gray color represents non-zero entries.
+
+\subsubsection{Performance comparison to a CPU implementation}
+\begin{figure}
+\centering
+\includegraphics[width=200pt]{Chapters/chapter19/fig/gpu-cpu.pdf}
+
+\caption{Performance of the SCOO on a GTX-580 and a CPU implementation using MKL performed on a Core-i7 2700K using 8 threads.}
+\label{fig:scoo-vs-cpu}
+\end{figure}
+
+We use the Intel MKL library 10.3 in order to compare SCOO performance to an optimized CPU implementation. MKL SpMV receives the input matrices in CSR format. The results are shown in Figure \ref{fig:scoo-vs-cpu}. Using a GTX-580, we achieve speedups ranging between 5.5 and 18 over MKL on a 4-core CPU with hyper-threading using 8 threads. Also note that the SCOO performance on a GTX-580 is around 1.5 times faster than on the C2075 due to the increased memory bandwidth and clock speed. The storage requirement for the \emph{rgg\_n\_2\_24\_s0} and \emph{uk-2002} matrices and associated input/output vectors slightly exceeds the 3 GB global memory of the GTX-580 and thus are not included.
+
+\section{Conclusion}
+\label{ch19:conclusion}
+In this chapter, we have presented our implementation of iterative SpMV for NFS matrices on GPUs with the CUDA programming language. Our GPU implementation takes advantage of the variety of sparseness properties in NFS matrices to produce suitable formats for different parts. The GPU implementation shows promising improvement over an optimized CPU implementation. As the size of integers in factorization projects is expected to increase further, the linear algebrea step of NFS will become an even bigger bottleneck. The size and sparseness of matrices generated by the NFS sieving step are growing significantly with the size of the integer to be factored. Thus, a big GPU cluster is required to accelerate the linear algebra step. However, in order to achieve scalability for bigger problem sizes, the amount of GPU RAM and data transfer bandwidth need to be increased in addition to the number of GPUs.
+
+We further adapted the proposed Sliced COO format to single-precision floating-point numbers and evaluated it with large and sparse matrices derived from other computational science applications. We have published our code at [-to be updated-].
+
+\putbib[Chapters/chapter19/biblio]
+
