-Project Oscar aims to provide an hardware and software architecture to
-estimate and control the deflection of cantilevers. The hardware part
-consists in a high-speed camera, linked on an embedded board hosting
-FPGAs. By the way, the camera output stream can be pushed directly
-into the FPGA. The software part is mostly the VHDL code that
-deserializes the camera stream, extracts profile and computes the
-deflection. Before focusing on our work to implement the phase
-computation, we give some general informations about FPGAs and the
-board we use.
-
-\subsection{FPGAs}
-
-A field-programmable gate array (FPGA) is an integrated circuit designed to be
-configured by the customer. A hardware description language (HDL) is used to
-configure a FPGA. FGPAs are composed of programmable logic components, called
-logic blocks. These blocks can be configured to perform simple (AND, XOR, ...)
-or complex combinational functions. Logic blocks are interconnected by
-reconfigurable links. Modern FPGAs contains memory elements and multipliers
-which enables to simplify the design and increase the speed. As the most complex
-operation operation on FGPAs is the multiplier, design of FGPAs should not used
-complex operations. For example, a divider is not an available operation and it
-should be programmed using simple components.
-
-FGPAs programming is very different from classic processors programming. When
-logic block are programmed and linked to performed an operation, they cannot be
-reused anymore. FPGA are cadenced more slowly than classic processors but they can
-performed pipelined as well as parallel operations. A pipeline provides a way
-manipulate data quickly since at each clock top to handle a new data. However,
-using a pipeline consomes more logics and components since they are not
-reusable, nevertheless it is probably the most efficient technique on FPGA.
-Parallel operations can be used in order to manipulate several data
-simultaneously. When it is possible, using a pipeline is a good solution to
-manipulate new data at each clock top and using parallelism to handle
-simultaneously several data streams.
-
-%% parler du VHDL, synthèse et bitstream
-\subsection{The board}
-
-The board we use is designed by the Armadeus compagny, under the name
-SP Vision. It consists in a development board hosting a i.MX27 ARM
-processor (from Freescale). The board includes all classical
-connectors : USB, Ethernet, ... A Flash memory contains a Linux kernel
-that can be launched after booting the board via u-Boot.
-
-The processor is directly connected to a Spartan3A FPGA (from Xilinx)
-via its special interface called WEIM. The Spartan3A is itself
-connected to a Spartan6 FPGA. Thus, it is possible to develop programs
-that communicate between i.MX and Spartan6, using Spartan3 as a
-tunnel. By default, the WEIM interface provides a clock signal at
-100MHz that is connected to dedicated FPGA pins.
-
-The Spartan6 is an LX100 version. It has 15822 slices, equivalent to
-101261 logic cells. There are 268 internal block RAM of 18Kbits, and
-180 dedicated multiply-adders (named DSP48), which is largely enough
-for our project.
-
-Some I/O pins of Spartan6 are connected to two $2\times 17$ headers
-that can be used as user wants. For the project, they will be
-connected to the interface card of the camera.
-
-\subsection{Considered algorithms}
-
-Two solutions have been studied to achieve phase computation. The
-original one, proposed by A. Meister and M. Favre, is based on
-interpolation by splines. It allows to compute frequency and
-phase. The second one, detailed in this article, is based on a
-classical least square method but suppose that frequency is already
-known.
-
-\subsubsection{Spline algorithm}
+In this section we present parts of the computing solution to the above
+requirements. The hardware part consists in a high-speed camera linked on an
+embedded board hosting two FPGAs. In this way, the camera output stream can be
+pushed directly into the FPGA. The software part is mostly the VHDL code that
+deserializes the camera stream, extracts profiles and computes the deflection.
+
+We first give some general information about FPGAs, then we
+describe the FPGA board we use for implementation and finally the two
+algorithms for phase computation are detailed. Presentation of VHDL
+implementations is postponned until Section \ref{sec:xp-test}.
+
+
+
+\subsection{Elements of FPGA architecture and programming}
+
+A field-programmable gate array (FPGA) is an integrated circuit designed to
+be configured by the customer. FGPAs are composed of programmable logic
+components, called configurable logic blocks (CLB). These blocks mainly
+contain look-up tables (LUT), flip/flops (F/F) and latches, organized in one
+or more slices connected together. Each CLB can be configured to perform
+simple (AND, XOR, ...) or complex combinational functions. They are
+interconnected by reconfigurable links. Modern FPGAs contain memory elements
+and multipliers which enable to simplify the design and to increase the
+performance. Nevertheless, all other complex operations like division and
+other functions like trigonometric functions are not available and must be
+built by configuring a set of CLBs. Since this is not an obvious task at
+all, tools like ISE~\cite{ISE} have been built to do this operation. Such a
+software can synthetize a design written in a hardware description language
+(HDL), maps it onto CLBs, place/route them for a specific FPGA, and finally
+produces a bitstream that is used to configure the FPGA. Thus, from the
+developer's point of view, the main difficulty is to translate an algorithm
+into HDL code, taking into account FPGA resources and constraints like clock
+signals and I/O values that drive the FPGA.
+
+Indeed, HDL programming is very different from classic languages like
+C. A program can be seen as a state-machine, manipulating signals that
+evolve from state to state. Moreover, HDL instructions can be executed
+concurrently. Signals may be combined with basic logic operations to
+produce new states that are assigned to another signal. States are mainly expressed as
+arrays of bits. Fortunately, libraries propose higher levels
+representations like signed integers, and arithmetic operations.
+
+Furthermore, even if FPGAs are cadenced more slowly than classic processors,
+they can perform pipelines as well as parallel operations. A pipeline
+consists in cutting a process in a sequence of small tasks, taking the same
+execution time. It accepts a new data at each clock top, thus, after a known
+latency, it also provides a result at each clock top. The drawback is that the
+components of a task are not reusable by another one. Nevertheless, this is
+the most efficient technique on FPGAs. Because of their architecture, it is
+also very easy to process several data concurrently. Finally, the best
+performance can be reached when several pipelines are operating on multiple
+data streams in parallel.
+
+\subsection{The FPGA board}
+
+The architecture we use is designed by the Armadeus Systems
+company. It consists in a development board called APF27 \textsuperscript{\textregistered}, hosting a
+i.MX27 ARM processor (from Freescale) and a Spartan3A (from
+Xilinx). This board includes all classical connectors as USB and
+Ethernet for instance. A Flash memory contains a Linux kernel that can
+be launched after booting the board via u-Boot. The processor is
+directly connected to the Spartan3A via its special interface called
+WEIM. The Spartan3A is itself connected to an extension board called
+SP Vision \textsuperscript{\textregistered}, that hosts a Spartan6 FPGA. Thus, it is
+possible to develop programs that communicate between i.MX and
+Spartan6, using Spartan3 as a tunnel. A clock signal at 100MHz (by
+default) is delivered to dedicated FPGA pins. The Spartan6 of our
+board is an LX100 version. It has 15,822 slices, each slice containing
+4 LUTs and 8 flip/flops. It is equivalent to 101,261 logic
+cells. There are 268 internal block RAM of 18Kbits, and 180 dedicated
+multiply-adders (named DSP48), which is largely enough for our
+project. Some I/O pins of Spartan6 are connected to two $2\times 17$
+headers that can be used for any purpose as to be connected to the
+interface of a camera.
+
+\subsection{Two algorithms for phase computation}
+
+As said in section \ref{sec:deflest}, $f$ is computed only once but
+the phase needs to be computed for each image. This is why, in this
+paper, we focus on its computation. The next section describes the
+original method, based on spline interpolation, and section
+\ref{sec:algo-square} presents the new one based on least
+squares. Finally, in section \ref{sec:algo-comp}, we compare the two
+algorithms from their FPGA implementation point of view.
+
+\subsubsection{Spline algorithm (SPL)}
+
