X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/dmems12.git/blobdiff_plain/5643f354956645b7d3592ac0e32af50cdf351155..0cd2856ba0791dd79a6d13292a5972bfbbc412f2:/dmems12.tex?ds=sidebyside

diff --git a/dmems12.tex b/dmems12.tex
index 314368e..572feb2 100644
--- a/dmems12.tex
+++ b/dmems12.tex
@@ -301,26 +301,37 @@ reconfigurable links. Modern FPGAs contain memory elements and
 multipliers which enable to simplify the design and to increase the
 performance. Nevertheless, all other complex operations, like
 division, trigonometric functions, $\ldots$ are not available and must
-be done by configuring a set of CLBs.
-
-Since this configuration is not obvious at all, it can be done via a
-framework that synthetize a design written in an hardware description
-language (HDL), and after, that place and route 
-
- is used to configure a FPGA.
-FGPAs programming  is very different  from classic processors  programming. When
-logic blocks are  programmed and linked to perform an  operation, they cannot be
-reused anymore.  FPGAs are cadenced more slowly than classic processors but they
-can perform pipeline  as well as parallel operations. A  pipeline provides a way
-to  manipulate  data  quickly  since  at   each  clock  top  it  handles  a  new
-data. However, using  a pipeline consumes more logics  and components since they
-are not  reusable. Nevertheless it is  probably the most  efficient technique on
-FPGA.   Parallel operations  can be  used in  order to  manipulate  several data
-simultaneously. When  it is  possible, using  a pipeline is  a good  solution to
-manipulate  new  data  at  each  clock  top  and  using  parallelism  to  handle
-simultaneously several pipelines in order to handle multiple data streams.
-
-%% parler du VHDL, synthÃ¨se et bitstream
+be done by configuring a set of CLBs. Since this configuration is not
+obvious at all, it can be done via a framework, like ISE. Such a
+software can synthetize a design written in an hardware description
+language (HDL), map it onto CLBs, place/route them for a specific
+FPGA, and finally produce a bitstream that is used to configre the
+FPGA. Thus, from the developper point of view, the main difficulty is
+to translate an algorithm in HDL code, taking account FPGA resources
+and constraints like clock signals and I/O values that drive the FPGA.
+
+Indeed, HDL programming is very different from classic languages like
+C. A program can be seen as a state-machine, manipulating signals that
+evolve from state to state. By the way, HDL instructions can execute
+concurrently. Basic logic operations are used to agregate signals to
+produce new states and assign it to another signal. States are mainly
+expressed as arrays of bits. Fortunaltely, libraries propose some
+higher levels representations like signed integers, and arithmetic
+operations.
+
+Furthermore, even if FPGAs are cadenced more slowly than classic
+processors, they can perform pipeline as well as parallel
+operations. A pipeline consists in cutting a process in sequence of
+small tasks, taking the same execution time. It accepts a new data at
+each clock top, thus, after a known latency, it also provides a result
+at each clock top. However, using a pipeline consumes more logics
+since the components of a task are not reusable by another
+one. Nevertheless it is probably the most efficient technique on
+FPGA. Because of its architecture, it is also very easy to process
+several data concurrently. When it is possible, the best performance
+is reached using parallelism to handle simultaneously several
+pipelines in order to handle multiple data streams.
+
 \subsection{The board}
 
 The board we use is designed by the Armadeus compagny, under the name
