From: couturie <couturie@carcariass.(none)>
Date: Tue, 18 Oct 2011 06:09:33 +0000 (+0200)
Subject: debut partie fpga
X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/dmems12.git/commitdiff_plain/bf7445b6734356ca388e58f07e1a1599c8a1df77?hp=-c

debut partie fpga
---

bf7445b6734356ca388e58f07e1a1599c8a1df77
diff --git a/dmems12.tex b/dmems12.tex
index ed1709b..eb96b5e 100644
--- a/dmems12.tex
+++ b/dmems12.tex
@@ -112,6 +112,19 @@ presented.
 \section{Measurement principles}
 \label{sec:measure}
 
+
+
+
+
+
+
+
+\subsection{Architecture}
+\label{sec:archi}
+%% description de l'architecture générale de l'acquisition d'images
+%% avec au milieu une unité de traitement dont on ne précise pas ce
+%% qu'elle est.
+
 In order to develop simple,  cost effective and user-friendly cantilever arrays,
 authors   of    ~\cite{AFMCSEM11}   have   developped   a    system   based   of
 interferometry. In opposition to other optical based systems, using a laser beam
@@ -139,16 +152,6 @@ fringes.
 
 
 
-
-
-
-
-\subsection{Architecture}
-\label{sec:archi}
-%% description de l'architecture générale de l'acquisition d'images
-%% avec au milieu une unité de traitement dont on ne précise pas ce
-%% qu'elle est.
-
 %% image tirée des expériences.
 
 \subsection{Cantilever deflection estimation}
@@ -222,6 +225,29 @@ $3000$ operations.
 
 \subsection{FPGA constraints}
 
+A field-programmable gate  array (FPGA) is an integrated  circuit designed to be
+configured by  the customer.  A hardware  description language (HDL)  is used to
+configure a  FPGA. FGPAs are  composed of programmable logic  components, called
+logic blocks.  These blocks can be  configured to perform simple (AND, XOR, ...)
+or  complex  combinational  functions.    Logic  blocks  are  interconnected  by
+reconfigurable  links. Modern  FPGAs  contains memory  elements and  multipliers
+which enables to simplify the design and increase the speed. As the most complex
+operation operation on FGPAs is the  multiplier, design of FGPAs should not used
+complex operations. For example, a divider  is not an available operation and it
+should be programmed using simple components.
+
+FGPAs programming  is very different  from classic processors  programming. When
+logic block are programmed and linked  to performed an operation, they cannot be
+reused anymore.  FPGA  are cadenced slowly than classic  processors but they can
+performed pipelined as  well as pipelined operations. A  pipeline provides a way
+manipulate data quickly  since at each clock top to handle  a new data. However,
+using  a  pipeline  consomes more  logics  and  components  since they  are  not
+reusable,  nevertheless it  is probably  the most  efficient technique  on FPGA.
+Parallel  operations   can  be  used   in  order  to  manipulate   several  data
+simultaneously. When  it is  possible, using  a pipeline is  a good  solution to
+manipulate  new  data  at  each  clock  top  and  using  parallelism  to  handle
+simultaneously several data streams.
+
 %% contraintes imposées par le FPGA : algo pipeline/parallele, pas d'op math complexe, ...