Merge branch 'master' of ssh://info.iut-bm.univ-fcomte.fr/hpcc2014

[hpcc2014.git] / hpcc.tex

diff --git a/hpcc.tex b/hpcc.tex
index 04c540346aa2c1d772aac9c74d7569de61725a16..22fa0472b9b38ef08bc932da3c7c42705fc9fb68 100644 (file)
--- a/hpcc.tex
+++ b/hpcc.tex
@@ -1,4 +1,3 @@
-

 \documentclass[conference]{IEEEtran}
 
 \usepackage[T1]{fontenc}
 \documentclass[conference]{IEEEtran}
 
 \usepackage[T1]{fontenc}


@@ -509,7 +508,7 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} =
 \begin{table}[!t]
   \centering
   \caption{Relative gain  of the multisplitting algorithm compared  to GMRES for
 \begin{table}[!t]
   \centering
   \caption{Relative gain  of the multisplitting algorithm compared  to GMRES for

-    different configurations with 2 clusters, each one composed of 50 nodes.}
+    different configurations with 2 clusters, each one composed of 50 nodes. Latency = $20$ms}

   \label{tab.cluster.2x50}
 
   \begin{mytable}{5}
   \label{tab.cluster.2x50}
 
   \begin{mytable}{5}


@@ -517,14 +516,14 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} =
     bandwidth (Mbit/s)
     & 5         & 5         & 5         & 5         & 5         \\
     \hline
     bandwidth (Mbit/s)
     & 5         & 5         & 5         & 5         & 5         \\
     \hline

-    latency (ms)
-    & 20      &  20      & 20      & 20      & 20      \\
-    \hline
+  %  latency (ms)
+   % & 20      &  20      & 20      & 20      & 20      \\
+    %\hline

     power (GFlops)
     & 1         & 1         & 1         & 1.5       & 1.5       \\
     \hline
     size $(N)$
     power (GFlops)
     & 1         & 1         & 1         & 1.5       & 1.5       \\
     \hline
     size $(N)$

-    & 62        & 62        & 62        & 100       & 100       \\
+    & $62^3$        & $62^3$        & $62^3$        & $100^3$       & $100^3$       \\

     \hline
     Precision
     & \np{E-5}  & \np{E-8}  & \np{E-9}  & \np{E-11} & \np{E-11} \\
     \hline
     Precision
     & \np{E-5}  & \np{E-8}  & \np{E-9}  & \np{E-11} & \np{E-11} \\


@@ -542,14 +541,14 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} =
     bandwidth (Mbit/s)
     & 50        & 50        & 50        & 50        & 50 \\ %       & 10        & 10 \\
     \hline
     bandwidth (Mbit/s)
     & 50        & 50        & 50        & 50        & 50 \\ %       & 10        & 10 \\
     \hline

-    latency (ms)
-    & 20      & 20      & 20      & 20      & 20 \\ %      & 0.03      & 0.01 \\
-    \hline
+    %latency (ms)
+    %& 20      & 20      & 20      & 20      & 20 \\ %      & 0.03      & 0.01 \\
+    %\hline

     Power (GFlops)
     & 1.5       & 1.5       & 1.5       & 1.5       & 1.5 \\ %      & 1         & 1.5 \\
     \hline
     size $(N)$
     Power (GFlops)
     & 1.5       & 1.5       & 1.5       & 1.5       & 1.5 \\ %      & 1         & 1.5 \\
     \hline
     size $(N)$

-    & 110       & 120       & 130       & 140       & 150  \\ %     & 171       & 171 \\
+    & $110^3$       & $120^3$       & $130^3$       & $140^3$       & $150^3$  \\ %     & 171       & 171 \\

     \hline
     Precision
     & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} \\ % & \np{E-5}  & \np{E-5} \\
     \hline
     Precision
     & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} \\ % & \np{E-5}  & \np{E-5} \\


@@ -715,7 +714,7 @@ tool to run efficiently an iterative parallel algorithm in asynchronous
 mode in a grid architecture. 
 
 In future works, we plan to extend our experimentations to larger scale platforms by increasing the number of computing cores and the number of clusters. 
 mode in a grid architecture. 
 
 In future works, we plan to extend our experimentations to larger scale platforms by increasing the number of computing cores and the number of clusters. 

-We will also have to increase the size of the input problem which will require the use of a more powerful simulation platform. At last, we expect to compare our simulation results to real execution results on real architectures in order to experimentally validate our study.
+We will also have to increase the size of the input problem which will require the use of a more powerful simulation platform. At last, we expect to compare our simulation results to real execution results on real architectures in order to better experimentally validate our study. Finally, we also plan to study other problems with the multisplitting method and other asynchronous iterative methods.

 
 \section*{Acknowledgment}
 
 
 \section*{Acknowledgment}